Abstract: An arrangement for generating addresses for interleaving/de-interleaving sequences (X1, X2, X3, . . . , XK) including a given number (K) of items, wherein each value for said given number (K) identifies a corresponding set of interleaving parameters (R, C, p, v). The arrangement has at least one memory unit wherein a plurality of records are stored, each record being indicative of a respective set of parameters (R, C, p, v) corresponding to at least one value for said given number (K). Sets of interleaving parameters (R, C, p, v) are thus available in the memory unit to be promptly and directly retrieved for all possible values of said given number of items (K). A preferred use is in turbo encoders/decoders for advanced telecommunications applications such as UMTS.

Abstract: A device for maintaining fine alignment between an incoming spread spectrum signal and a locally generated code in a digital communication receiver comprises:—delay line (56) for storing a plurality of consecutive samples (E?1, E, M, L, L+1) of the incoming spread spectrum signal;—three digitally controlled interpolators (24, 26, 28) for determining by interpolation between consecutive samples an interpolated early sample (e), an interpolated middle sample (m) and an interpolated late sample (1);—two correlators (30, 32) for calculating an error signal (?) as the difference between the energy of the symbols computed from the interpolated early (e) and late (1) samples;—a circuit for generating a control signal (SOUT?) for controlling the interpolation phase of the digitally controlled interpolator (24) for the early sample (e), and—a digital non-linear filter (68), for smoothing the control signal (SOUT?) of the interpolator (24) for the early sample (e), enabling the update operation of the control signal on

Abstract: A method for the synchronization of a digital telecommunication receiver comprises the steps of:—storing a plurality of consecutive samples E?1, B, M, 1, L+1 of an incoming spread spectrum signal in a delay line 56;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a first digitally controlled interpolator 26, an interpolated early sample (e) anticipating an optimal sampling time instant;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a second digitally controlled interpolator 24, an interpolated middle sample (m) corresponding to the optimal sampling time instant;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a third digitally controlled interpolator 28, an interpolated late sample (1) delayed with respect to the optimal sampling time instant;—calculating an error signal ? as the difference between the energy of the symbols com

Abstract: A spread spectrum digital communication receiver, of the type comprising an input memory buffer (16) for storing samples of an input signal (y(k)) and a code generator circuit (30) for generating a re-generated user code, incorporates a device (24) for the estimation of a channel delay profile comprises: a basic correlator (32) having a first input (41) for sequentially reading from a memory location of the input memory buffer (16) a plurality of samples of the input signal (y(k)), a second input (43) for receiving from the code generator circuit (30) a re-generated user code, and an output terminal for generating, by means of a correlation operation between the plurality of samples of the input signal and the regenerated user code, a first value of the channel delay profile energy (DP(1)); and a memory controller circuit (36) for addressing said the memory buffer (16) so that the first input (41) of the basic correlator (32) is successively fed with the content of several memory locations of the memory buffe

Abstract: An arrangement for generating addresses for interleaving/de-interleaving sequences (X1, X2, X3, . . . , XK) including a given number (K) of items, wherein each value for said given number (K) identifies a corresponding set of interleaving parameters (R, C, p, v). The arrangement has at least one memory unit wherein a plurality of records are stored, each record being indicative of a respective set of parameters (R, C, p, v) corresponding to at least one value for said given number (K). Sets of interleaving parameters (R, C, p, v) are thus available in the memory unit to be promptly and directly retrieved for all possible values of said given number of items (K). A preferred use is in turbo encoders/decoders for advanced telecommunications applications such as UMTS.

Abstract: An iterative multiplier circuit (10) comprises modules (15 to 18) that subdivide the respective input signals (Zn, Jn) into a first part (msb(Zn), msb(Jn)) that is the power of 2 immediately lower or equal to the input signal and a second part (Zn—msb(Zn), Jn—msb(Jn)) corresponding to the difference between the input signal and the aforesaid first part. A shift module (19) generates a respective output signal through shift operations that implement the multiplication operation for numbers that are powers of 2. The circuit operates according to a general iterative scheme in which at each step three components of the output signal (X,Y) are computed, corresponding to the product of two numbers that are powers of 2 and to two products in which at least one of the factors is a power of 2. The number of steps in the iteration scheme is controllable, thus allowing to vary the accuracy with which the output value (X,Y) is calculated.

Abstract: An iterative power raising circuit, such as a squarer (10) comprises a module (13, 14) able to subdivide the respective input signal (Zn) into a first part (msb(Zn)) that is the power of 2 immediately lower than or equal to the input signal and a second part (Zn−msb(Zn)) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme is selectively controllable in order selectively to vary the precision with which the output value (Y) is calculated.

Abstract: The present invention relates to a module 50 for generating integrated decoding circuits for use, in particular, in turbo devices, to the method for defining the characteristics of and generating convolutional decoding circuits, and to the circuit that can be obtained with said module 50. The module 50 is parametric and, thanks to this feature, makes it possible to generate decoding circuits having different performance characteristics which are such that they can be used in turbo devices employing different decoding modes and different architectures. In addition, the module 50 makes it possible to generate decoding circuits whose distinguishing feature is that they can manage a plurality of generator polynomials selectively and can thus also be used in asymmetrical turbo devices.

Abstract: Models destined for verification are described at the level of synthesizable description (for example VHDL). The synthesizable description (200) is automatically converted (300) into a C++ model (200′). This allows verification of the correctness of the synthesizable description by comparing the results of a verification carried out on the original description from the cell in C++ with the results of a similar verification of the C++ model obtained by automatic conversion of the synthesizable description. It is also possible to make the C++ model obtained by automatic conversion (200′) to interact with a system model including blocks (201, 202, 203) of a system model at C++ level, in particular with the possibility of producing concurrent events that occur in correspondence with a main timing signal source.