Patents by Inventor Donato Forlenza
Donato Forlenza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7574644Abstract: A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.Type: GrantFiled: June 25, 2005Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Donato Forlenza, Franco Molika, Phillip J. Nigh
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Publication number: 20080091999Abstract: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.Type: ApplicationFiled: December 14, 2007Publication date: April 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd BURDINE, Donato FORLENZA, Orazio FORLENZA, William HURLEY, Phong TRAN
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Publication number: 20070260926Abstract: Exemplary embodiments include a static and dynamic test generation and simulation method including: analyzing a logic model; identifying a logic structure in the logic model whose input/output signal can be assigned to a particular logical value and remain fixed during a fault simulation test; and running the fault simulation test to check the logic model for faults.Type: ApplicationFiled: April 13, 2006Publication date: November 8, 2007Applicant: International Business Machines CorporationInventors: Donato Forlenza, Orazio Forlenza, Mary Kusko
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Publication number: 20070011523Abstract: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.Type: ApplicationFiled: June 9, 2005Publication date: January 11, 2007Applicant: International Business Machines CorporationInventors: Todd Burdine, Donato Forlenza, Orazio Forlenza, William Hurley, Phong Tran
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Patent number: 7017095Abstract: A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.Type: GrantFiled: July 10, 2002Date of Patent: March 21, 2006Assignee: International Business Machines CorporationInventors: Donato Forlenza, Franco Motika, Phillip J. Nigh
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Publication number: 20050289426Abstract: A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.Type: ApplicationFiled: June 25, 2005Publication date: December 29, 2005Inventors: Donato Forlenza, Franco Molika, Phillip Nigh
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Publication number: 20050229057Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.Type: ApplicationFiled: April 8, 2004Publication date: October 13, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adrian Anderson, Todd Burdine, Donato Forlenza, Orazio Forlenza, William Hurley, Phong Tran
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Publication number: 20050160339Abstract: Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Rather than store the entire set of test parameters for each of a plurality of test sequences to be performed, as with conventional test systems, embodiments of the present invention only store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.Type: ApplicationFiled: January 15, 2004Publication date: July 21, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donato Forlenza, Orazio Forlenza, William Hurley, Bryan Robbins
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Publication number: 20050138514Abstract: An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.Type: ApplicationFiled: December 4, 2003Publication date: June 23, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd Burdine, Donato Forlenza, Orazio Forlenza, William Hurley, Steven Michnowski, James Webb
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Publication number: 20040010741Abstract: A method of diagnosing complex semiconductor device functional testing failures by combining deterministic and functional testing with diagnostic techniques. The method determines the failing logic locations by creating a new test pattern based on the functional failure by transforming a functional pattern into a scan deterministic pattern so that existing diagnostic tools can also be used to determine the location of and type of error in the failing circuit without impacting manufacturing test. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector.Type: ApplicationFiled: July 10, 2002Publication date: January 15, 2004Applicant: International Business Machines CorporationInventors: Donato Forlenza, Franco Motika, Phillip J. Nigh