Abstract: A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Abstract: A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Abstract: A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Abstract: The present invention relates to DEIS (Dual Electron Injector Structure) EAROM (Electrically Alterable Read Only Memory) devices which utilize a silicon-rich, silicon dioxide insulator between injectors which has an excess of silicon therein which is less than the excess of silicon in the silicon rich, silicon dioxide injectors. The device does not depart in any way from known DEIS EAROM devices except that the insulator layer between the injectors is rendered conductive to a desired degree by causing a compound insulator like SiO.sub.2 to be off-stoichiometry during deposition so that the resulting insulator becomes silicon rich. Alternatively, the insulator may be deposited together with another metal which renders the insulator conductive or a metallic specie may be added to the insulator by diffusion or ion implantation after the insulator is formed.

Abstract: A semiconductor structure that includes a semiconductor substrate; an insulating layer adjacent the substrate; a semiconductor or conductor grid adjacent the insulating layer; another insulating layer adjacent the semiconductor grid; and an injector adjacent the second insulating layer. The injector includes a layer of silicon-rich insulator material and a layer of semiconductor material adjacent the silicon-enriched material.

Abstract: A two carrier dual injector semiconductor apparatus utilizing a pair of injector gates for simultaneously injecting holes and electrons into a series stack of insulator layers. The stacked insulator layers which may be arranged in a MIM or MIS configuration have injecting layers near opposing metal gates for injecting either electrons as holes into the insulator layers depending upon the polarity of the applied bias voltage. The apparatus is capable of high-current low-voltage carrier injection while maintaining a stable trapped spaced charge within the stack of insulator layers.

Abstract: Juxtaposing, on a common p-type substrate, an array of field effect transistor memory cells each including a random access memory dynamic RAM device comprising a floating gate portion and a storage node, and each including also a non-volatile unit comprising a double electron injector structure (DEIS) adjacent the floating gate portion, but remote from the storage node, provides a simple, low current dynamic random access memory array with non-volatile restart capability in case of power interruption.The non-volatile unit in each memory cell shares the control gate and substrate in common with the dynamic RAM device and thus shares access to the floating gate but is remote from the storage node. Situated between the floating gate and the substrate is a silicon-rich DEIS stack. During normal operation, the device functions as a dynamic RAM device. When non-volatile storage is required, electrons are written into the floating gate by raising the voltage on the control gate.

Abstract: This invention provides improved non-volatile semiconductor memories which include a one device dynamic volatile memory circuit having a switching device, a storage capacitor and a non-volatile floating gate device disposed between the storage node and the switching device. The non-volatile floating gate device has a floating gate, a floating gate FET, a control gate and a voltage divider having first and second serially-connected capacitors, with the floating gate being disposed at the common point between the first and second capacitors. One of the capacitors includes a dual charge or electron injector structure and the capacitance of this capacitor has a value substantially less than that of the other capacitor.

Abstract: New non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structures are described. With the graded or stepped insulator, electrons or holes can be injected from the gate electrode at low to moderate applied fields. The carriers flow under the applied field into a wide energy band gap insulator having a prescribed charge trapping layer. This layer captures and stores electrons (write operation) or holes (erase operation) with 100% efficiency.

Abstract: A high field capacitor structure includes an insulating layer having a carrier trapping region between two electrodes. The trapping region improves electric breakdown characteristics of the capacitor structure and is particularly useful in avoiding the low breakdown voltages and high leakage currents normally encountered in structures with asperities, such as SiO.sub.2 over poly Si. The trapping region can be formed by chemical vapor deposition (CVD) process, by evaporation or by ion implantation. The trapping region is close to the Si, but far enough away to eliminate the possibility of reverse tunneling from discharging the traps in the absence of an applied voltage.

Abstract: A graded oxide MIM or MIS structure employs band gap grading of the insulator oxide so that holes or electrons (depending on voltage bias) can be injected into the insulator oxide under moderate electric field conditions from the contact at one interface. Electron or hole injection from the opposite interface is blocked due to the larger insulator band gap near this interface. A graded oxide metal-silicon dioxide-silicon (MGOS) semiconductor structure may be fabricated by forming several pyrolytic or CVD SiO.sub.2 layers over a relatively thick thermal SiO.sub.2 layer, with the pyrolytic SiO.sub.2 layers having sequentially increasing excess Si content. This structure may also be fabricated by controlled Si ion implantation in the thermal SiO.sub.2 layer.

Abstract: New non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structures are described. With the graded or stepped insulator, electrons or holes can be injected from the gate electrode at low to moderate applied fields. The carriers flow under the applied field into a wide energy band gap insulator having a prescribed charge trapping layer. This layer captures and stores electrons (write operation) or holes (erase operation) with 100% efficiency.