Abstract: An electronic device includes a first counting circuit configured to generate a first counting signal based on a comparison signal that is generated by comparing a first row address after the start of a first bootup operation and first fuse data that are generated by a first rupture operation, a second counting circuit configured to generate a second counting signal based on the comparison signal that is generated by comparing a second row address after the start of a second bootup operation and second fuse data that are generated by a second rupture operation, and a repair comparison circuit configured to generate a repair detection signal for detecting whether the first and second rupture operations are additionally performed by comparing the first counting signal with the second counting signal and configured to output the repair detection signal.

Abstract: An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.

Abstract: An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.

Abstract: A semiconductor device includes a flag generation circuit configured to receive region fuse data and used fuse data which are generated from a fuse set selected based on a fuse set selection signal among from fuse sets and generate a bank resource flag to control a repair operation for a bank on which a repair operation has not been performed, based on the region fuse data and the used fuse data. The semiconductor device also includes a repair control circuit configured to control the repair operation for banks sharing the fuse sets based on the bank resource flag.

Abstract: An apparatus includes a selection data generation circuit configured to generate selection data from fuse data or generate the selection data having a preset test input pattern, depending on whether a failure test is entered; and a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern.

Abstract: An apparatus includes a boot-up control circuit configured to, when a first boot-up operation is performed, latch first fuse data by receiving the first fuse data and fuse information from a fuse circuit and configured to, when a second boot-up operation is performed, latch second fuse data by receiving the second fuse data from the fuse circuit based on the fuse information; and a rupture control circuit configured to store a failure address as the second fuse data by rupturing the fuse circuit based on the fuse information.

Abstract: An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.

Abstract: A semiconductor device includes a flag generation circuit configured to receive region fuse data and used fuse data which are generated from a fuse set selected based on a fuse set selection signal among from fuse sets and generate a bank resource flag to control a repair operation for a bank on which a repair operation has not been performed, based on the region fuse data and the used fuse data. The semiconductor device also includes a repair control circuit configured to control the repair operation for banks sharing the fuse sets based on the bank resource flag.

Abstract: A neuromorphic device according to various embodiments of the present disclosure includes a recognizing unit suitable for recognizing information based on a plurality of learned results to generate a plurality of recognition signals, a maximum value extracting unit suitable for respectively extracting values of the plurality of recognition signals and extracting a recognition signal having a maximum value among the plurality of recognition signals, and a control unit suitable for processing the information based on the recognition signal having the maximum value.

Abstract: An apparatus includes a boot-up control circuit configured to, when a first boot-up operation is performed, latch first fuse data by receiving the first fuse data and fuse information from a fuse circuit and configured to, when a second boot-up operation is performed, latch second fuse data by receiving the second fuse data from the fuse circuit based on the fuse information; and a rupture control circuit configured to store a failure address as the second fuse data by rupturing the fuse circuit based on the fuse information.

Abstract: An apparatus includes a selection data generation circuit configured to generate selection data from fuse data or generate the selection data having a preset test input pattern, depending on whether a failure test is entered; and a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern.

Abstract: The present invention relates to a novel alpha-1,3-glucanase, and more particularly, to a novel alpha-1,3-glucanase from Trichoderma harzianum, a gene encoding the same, a recombinant vector and recombinant microorganism comprising the gene, and a method of producing an alpha-1,3-glucanase using the recombinant microorganism. The novel alpha-1,3-glucanase according to the present invention can effectively degrade mutan, which is a component of a microbial biofilm, and thus it can be used in oral hygiene products and the medical field.

Abstract: The present invention relates to a novel alpha-1,3-glucanase, and more particularly, to a novel alpha-1,3-glucanase from Trichoderma harzianum, a gene encoding the same, a recombinant vector and recombinant microorganism comprising the gene, and a method of producing an alpha-1,3-glucanase using the recombinant microorganism. The novel alpha-1,3-glucanase according to the present invention can effectively degrade mutan, which is a component of a microbial biofilm, and thus it can be used in oral hygiene products and the medical field.

Abstract: A neuromorphic device according to various embodiments of the present disclosure includes a recognizing unit suitable for recognizing information based on a plurality of learned results to generate a plurality of recognition signals, a maximum value extracting unit suitable for respectively extracting values of the plurality of recognition signals and extracting a recognition signal having a maximum value among the plurality of recognition signals, and a control unit suitable for processing the information based on the to recognition signal having the maximum value.

Abstract: A semiconductor memory device includes: a memory array region including normal memory cells and redundant memory cells; a fuse circuit including fuse cells for programming repair addresses, outputting fuse data including the programmed repair addresses and fuse enable signals in response to a boot-up signal; a fuse information storage including N latch circuits for storing the fuse data, wherein each of the N latch circuits drives fuse lines assigned from N fuse lines based on the fuse enable signals and a comparison result of the corresponding repair addresses and an input address; and a repair control circuit generating a repair activation signal and an M-bit repair control signal based on signals of the N fuse lines, and outputting the M-bit repair control signal to multiple address lines by selectively mapping the M-bit repair control signal to some bits of the input address, based on the repair activation signal.

Abstract: An organic light emitting diode display including: a substrate; a plurality of first signal lines on the substrate extending in a first direction; a first insulating layer covering the substrate and the first signal lines; a plurality of auxiliary signal lines formed on the first insulating layer and overlapping the first signal lines; a second insulating layer covering the auxiliary signal lines; a plurality of first signal line connecting members formed on the second insulating layer while overlapping parts of the auxiliary signal lines; a plurality of second signal lines crossing the first signal lines; a plurality of switching transistors and a plurality of driving transistors connected with the first signal lines and the second signal lines; and a plurality of organic light emitting diodes electrically connected to the driving transistors, where the first signal line connecting members connect the first signal lines to the auxiliary signal lines.

Abstract: A memory device may include a plurality of first sense amplifiers including a plurality of corresponding first input terminals, a plurality of second sense amplifiers including a plurality of corresponding second input terminals, the plurality of first and second sense amplifiers being suitable for amplifying data received through the respective plurality of first and second input terminals, and for outputting the amplified data which include first and second data outputted by the plurality of first sense amplifiers and third and fourth data outputted by the plurality of second sense amplifiers; a plurality of first pipe latches suitable for latching and outputting the first and second data at a specific interval; a plurality of second pipe latches suitable for latching and outputting the third and fourth data at a specific interval; and an input/output line coupled to the plurality of first and second pipe latches, suitable for outputting the first, second, third and fourth data.

Abstract: A clock control device is disclosed, which relates to a technology for changing a rising or falling edge trigger. The clock control device includes: a flip-flop configured to latch data in response to a delay clock signal; and a clock controller configured to output the delay clock signal by delaying a clock signal, and control the data to be triggered at a falling edge of the clock signal when the clock signal is input at a time earlier than the data.

Abstract: A clock control device is disclosed, which relates to a technology for changing a rising or falling edge trigger. The clock control device includes: a flip-flop configured to latch data in response to a delay clock signal; and a clock controller configured to output the delay clock signal by delaying a clock signal, and control the data to be triggered at a falling edge of the clock signal when the clock signal is input at a time earlier than the data.

Abstract: A self-refresh control device may be provided. The self-refresh control device may include a refresh signal output circuit configured to generate self-refresh signals with an oscillator and provide a refresh signal. The self-refresh control device may begin a self-refresh mode in response to a clock enable signal and a self-refresh signal within a self-refresh entry period, and may prevent performance of a new self-refresh operation by delaying an additional self-refresh signal until after the self-refresh entry period has ended.