Abstract: An MPEG decoder and an MPEG decoding method with two memory controllers is capable of separately controlling compressed data and decoded data. An MPEG decoder decodes a compressed input data formatted in an MPEG type. The MPEG decoder comprises a compressed data memory controller and a decoded data memory controller. The compressed data memory controller is coupled to a compressed data memory and controls the compressed data. The decoded data memory controller is coupled to a decoded data memory, and controls the decoded data. Since the compressed data flow and the decoded data flow are divided, the memory transfer rate is increased, and also the memory control is simple. In addition, the compressed data are able to be stored within the MPEG decoder. Therefore, the high-performance of the MPEG decoder and the high quality of the image are possible.

Abstract: The present invention provides a method and an apparatus for performing multiply operation of floating point data in 2-cycle pipeline scheme, which can be applied to pipelined data path so that it is always capable of processing floating point data as long as the data is not contiguous, for reducing the area of the multiplier by reducing the number of basic cells used to 1/3 of that of basic cells used in conventional techniques.

Abstract: This invention is developed to provide a computing system which can carry out a high speed access to a cache memory within one cycle even though data needed to be read is on the border of two pages. To realize the high speed computing system accessible to a split line on the border of two pages within one cycle, the computing system includes a translation lookaside buffer (TLB) which is designed to have a dual port structure, a prefetcher and a data/code cache memory which is improved for supporting the translated lookaside buffer (TLB).

Abstract: Memory management unit with address translation function improves the translation speed for virtual addresses and minimizes the deviation in response time. The memory management unit translates partially and entirely the virtual address into an physical address by using four extended auxiliary caches. And the memory management unit performs table walks for the zest part of the virtual address which is not translated, by using four tables contained in main memory.