Patents by Inventor Dong-Byum Kim

Dong-Byum Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060024592
    Abstract: A mask for making a polysilicon structure includes a transmitting area that transmits light and a blocking area that has a metal layer and a semiconductor layer deposited in an alternating manner at least once. The blocking area blocks light. The mask is subject to less thermal stress from the light (e.g., a laser beam) and therefore has a longer life span compared to a conventional mask.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 2, 2006
    Inventor: Dong-byum Kim
  • Publication number: 20050181553
    Abstract: A light having a pulse frequency higher than about 300 Hz is generated. The light is irradiated on an amorphous silicon thin film for a predetermined time period to form an initial polysilicon crystal. The light is transported in a predetermined direction to grow the initial polysilicon crystal. A laser beam having a decreased output energy is irradiated on the amorphous silicon thin film to crystallize the amorphous silicon thin film to a polysilicon thin film so that the load of an apparatus for generating the laser beam is decreased, and the lifetime of the apparatus for generating the laser beam increases.
    Type: Application
    Filed: May 13, 2004
    Publication date: August 18, 2005
    Inventors: Dong-Byum Kim, Se-Jin Chung, Ui-Jin Chung
  • Publication number: 20050151196
    Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.
    Type: Application
    Filed: February 3, 2005
    Publication date: July 14, 2005
    Inventors: Hyun-Jae Kim, Sook-Young Kang, Dong-Byum Kim, Su-Gyeong Lee, Myung-Koo Kang
  • Patent number: 6906349
    Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: June 14, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jae Kim, Sook-Young Kang, Dong-Byum Kim, Su-Gyeong Lee, Myung-Koo Kang
  • Publication number: 20040201019
    Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.
    Type: Application
    Filed: January 8, 2004
    Publication date: October 14, 2004
    Inventors: Hyun-Jae Kim, Sook-Young Kang, Dong-Byum Kim, Su-Gyeong Lee, Myung-Koo Kang