Patents by Inventor Dong-Chan Lim
Dong-Chan Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11929366Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.Type: GrantFiled: June 22, 2022Date of Patent: March 12, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Sunyoung Noh, Wandon Kim, Hyunbae Lee, Donggon Yoo, Dong-Chan Lim
-
Publication number: 20240071712Abstract: An ion beam deposition method includes placing a substrate into an ion beam deposition apparatus, irradiating an ion beam from an ion beam source toward a target plate, and rotating the target plate during the irradiating of the ion beam. The target plate includes a first region that includes a first material, and a second region that includes a second material different from the first material.Type: ApplicationFiled: July 26, 2023Publication date: February 29, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: SeungWan YOO, Jeongyeon LEE, Dohyung KIM, Jaehong PARK, Dong-Chan LIM
-
Publication number: 20240062996Abstract: An ion beam source including a plasma chamber including a plasma generating space, a plasma generator configured to generate plasma in the plasma generating space, a first grid connected to the plasma chamber, a second grid connected to the plasma chamber, and a first grid driver connected to the first grid. The first grid driver may be configured to move the first grid relative to the second grid.Type: ApplicationFiled: August 15, 2023Publication date: February 22, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: SeungWan YOO, Jeongyeon LEE, Dohyung KIM, Jaehong PARK, Dong-Chan LIM
-
Patent number: 11804472Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.Type: GrantFiled: March 2, 2021Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Seung Lee, Kwang-Jin Moon, Tae-Seong Kim, Dae-Suk Lee, Dong-Chan Lim
-
Patent number: 11791137Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.Type: GrantFiled: April 22, 2020Date of Patent: October 17, 2023Inventors: Hakseung Lee, Ho-Jin Lee, Dong-Chan Lim, Jinnam Kim, Kwangjin Moon
-
Patent number: 11728297Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.Type: GrantFiled: May 20, 2021Date of Patent: August 15, 2023Inventors: Ju-il Choi, Kwang-jin Moon, Ju-bin Seo, Dong-chan Lim, Atsushi Fujisaki, Ho-jin Lee
-
Patent number: 11705386Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.Type: GrantFiled: February 17, 2022Date of Patent: July 18, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang Wuk Park, Sung Dong Cho, Eun Ji Kim, Hak Seung Lee, Dae Suk Lee, Dong Chan Lim, Sang Jun Park
-
Publication number: 20230187393Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.Type: ApplicationFiled: February 13, 2023Publication date: June 15, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Ju-il CHOI, Kwangjin Moon, Sujeong Park, JuBin Seo, Jin Ho An, Dong-chan Lim, Atsushi Fujisaki
-
Patent number: 11600552Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: GrantFiled: June 10, 2021Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Bin Seo, Su-Jeong Park, Tae-Seong Kim, Kwang-Jin Moon, Dong-Chan Lim, Ju-Il Choi
-
Patent number: 11581279Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.Type: GrantFiled: April 13, 2021Date of Patent: February 14, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-il Choi, Kwangjin Moon, Sujeong Park, JuBin Seo, Jin Ho An, Dong-chan Lim, Atsushi Fujisaki
-
Publication number: 20220352156Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.Type: ApplicationFiled: June 22, 2022Publication date: November 3, 2022Inventors: Sunyoung NOH, Wandon KIM, Hyunbae LEE, Donggon YOO, Dong-Chan LIM
-
Patent number: 11488860Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: GrantFiled: July 24, 2020Date of Patent: November 1, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Su-jeong Park, Dong-chan Lim, Kwang-jin Moon, Ju-bin Seo, Ju-Il Choi, Atsushi Fujisaki
-
Patent number: 11374001Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.Type: GrantFiled: April 17, 2020Date of Patent: June 28, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sunyoung Noh, Wandon Kim, Hyunbae Lee, Donggon Yoo, Dong-Chan Lim
-
Publication number: 20220173016Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.Type: ApplicationFiled: February 17, 2022Publication date: June 2, 2022Inventors: Kwang Wuk PARK, Sung Dong CHO, Eun Ji KIM, Hak Seung LEE, Dae Suk LEE, Dong Chan LIM, Sang Jun PARK
-
Patent number: 11289402Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.Type: GrantFiled: November 8, 2019Date of Patent: March 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Wuk Park, Sung Dong Cho, Eun Ji Kim, Hak Seung Lee, Dae Suk Lee, Dong Chan Lim, Sang Jun Park
-
Publication number: 20210296211Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: ApplicationFiled: June 10, 2021Publication date: September 23, 2021Inventors: Ju-Bin SEO, Su-Jeong Park, Tae-Seong Kim, Kwang-Jin Moon, Dong-Chan Lim, Ju-Il Choi
-
Publication number: 20210272918Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Inventors: Ju-il Choi, Kwang-jin Moon, Ju-bin Seo, Dong-chan Lim, Atsushi Fujisaki, Ho-jin Lee
-
Publication number: 20210233879Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ju-il CHOI, Kwangjin MOON, Sujeong PARK, JuBin SEO, Jin Ho AN, Dong-chan LIM, Atsushi FUJISAKI
-
Patent number: 11069597Abstract: Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.Type: GrantFiled: March 27, 2019Date of Patent: July 20, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-suk Lee, Hak-seung Lee, Dong-chan Lim, Tae-seong Kim, Kwang-jin Moon
-
Patent number: 11043445Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: GrantFiled: April 17, 2019Date of Patent: June 22, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Bin Seo, Su-Jeong Park, Tae-Seong Kim, Kwang-Jin Moon, Dong-Chan Lim, Ju-Il Choi