Abstract: The present application relates to a sweetener including an oligosaccharide having increased acid resistance, a food composition including the same, and a method of increasing acid resistance of an oligosaccharide of an oligosaccharide-containing sweetener including applying allulose to the oligosaccharide.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: The present invention relates to an image encoding and decoding technique, and more particularly, to an image encoder and decoder using unidirectional prediction. The image encoder includes a dividing unit to divide a macro block into a plurality of sub-blocks, a unidirectional application determining unit to determine whether an identical prediction mode is applied to each of the plurality of sub-blocks, and a prediction mode determining unit to determine a prediction mode with respect to each of the plurality of sub-blocks based on a determined result of the unidirectional application determining unit.

Abstract: A display device includes a display panel including a rear surface and a front surface, where the front surface is provided with a display surface and including a folding axis extending in a first direction, a first barrier member disposed on the rear surface of the display panel and having a modulus of about 1 GPa to about 300 GPa, a first coupling member disposed on a rear surface of the first barrier member, and a metal plate disposed on a rear surface of the first coupling member and including a first plate portion and a second plate portion which are arranged in a second direction crossing the first direction and a connection portion connecting the first plate portion and the second plate portion, where the first coupling member does not overlap the connection portion in a plan view.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: A protective window includes a glass substrate which faces a display surface of an image-generating panel and has a thickness of about 20 micrometers to about 80 micrometers; a protective film which faces the display surface of the image-generating panel with the glass substrate therebetween; an adhesive layer which is between the protective film and the glass substrate and combines the protective film with the glass substrate; and a protective layer which covers an edge portion of the glass substrate. A thickness of the protective layer which covers the edge portion of the glass substrate is equal to or less than about ? of a thickness of the adhesive layer which combines the protective film with the glass substrate.

Abstract: A flexible display device is provided. A flexible display device according to one embodiment of the present invention comprises a body, a moving plate, a first pulley, a second pulley, a driving track and a flexible display. The flexible display is coupled to outer surfaces of the moving plate and the driving track, and the driving track forms a continuous track shape by itself or together with the moving plate. Therefore, provided is the flexible display device in which a constant tension can be maintained over the entire section of the driving track while the moving plate and the driving track support the flexible display, the occurrence of spring back in the flexible display can be minimized, and damage caused by unevenness of the flexible display, and the like, can be prevented.

Abstract: Disclosed is a pedestal heater block for a chemical vapor deposition machine, in which a structure intended for causing a vacuum to be applied is installed on a surface so that a wafer can be fixed by vacuum absorption, and which comprises: gas supply holes distributed to supply gas for temperature uniformity onto a back side of the wafer; and a hot wire configured to apply heat to the wafer, wherein the hot wire is installed to have higher installation density in a central part of the heater block which is a position corresponding to a central part of the wafer than that in a neighborhood part which is an outer side of the heater block.

Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N?1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N?1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.

Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N?1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N?1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.

Abstract: A clock switch device includes a controller and a switching circuit. The controller sets a clock switch period using a control signal when a logic level of a mode signal is changed. The switching circuit receives a first clock signal, a second clock signal and an auxiliary clock signal. The switching circuit, based on the control signal, outputs one clock signal between the first clock signal and the second clock signal as a glitch free clock signal before the clock switch period, stops outputting the one clock signal and outputs the auxiliary clock signal as the glitch free clock signal during the clock switch period, and stops outputting the auxiliary clock signal and outputs another clock signal between the first clock signal and the second clock signal as the glitch free clock signal after the clock switch period.

Abstract: A clock switch device includes a controller and a switching circuit. The controller sets a clock switch period using a control signal when a logic level of a mode signal is changed. The switching circuit receives a first clock signal, a second clock signal and an auxiliary clock signal. The switching circuit, based on the control signal, outputs one clock signal between the first clock signal and the second clock signal as a glitch free clock signal before the clock switch period, stops outputting the one clock signal and outputs the auxiliary clock signal as the glitch free clock signal during the clock switch period, and stops outputting the auxiliary clock signal and outputs another clock signal between the first clock signal and the second clock signal as the glitch free clock signal after the clock switch period.

Abstract: A display interface system includes a display transmitter and a display receiver. The display transmitter transmits a control pattern having image type information about a type of an image to be displayed and selectively transmits image data according to the type of the image to be displayed. The display receiver receives the control pattern and selectively receives the image data based upon the image type information, reducing power consumption.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.

Abstract: A display interface system includes a display transmitter and a display receiver. The display transmitter transmits a control pattern having image type information about a type of an image to be displayed and selectively transmits image data according to the type of the image to be displayed. The display receiver receives the control pattern and selectively receives the image data based upon the image type information, reducing power consumption.

Abstract: A voltage-drop measuring circuit is capable of measuring a voltage-drop of a power supply voltage caused by a resistance component of a power line. The voltage-drop measuring circuit includes a sensing circuit and a voltage-drop detecting circuit. The sensing circuit includes a sensor configured to generate a sensing voltage received by the sensor from a power pad through a power line between the sensor and the power pad. The voltage-drop detecting circuit is arranged in a neighborhood of a power pad, and is configured to generate a reference voltage, compare the sensing voltage with the reference voltage to detect the voltage-drop, and generate a detecting signal in accordance with the voltage-drop.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.