Abstract: Disclosed is a pedestal heater block for a chemical vapor deposition machine, in which a structure intended for causing a vacuum to be applied is installed on a surface so that a wafer can be fixed by vacuum absorption, and which comprises: gas supply holes distributed to supply gas for temperature uniformity onto a back side of the wafer; and a hot wire configured to apply heat to the wafer, wherein the hot wire is installed to have higher installation density in a central part of the heater block which is a position corresponding to a central part of the wafer than that in a neighborhood part which is an outer side of the heater block.

Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N?1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N?1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.

Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N?1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N?1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.

Abstract: A clock switch device includes a controller and a switching circuit. The controller sets a clock switch period using a control signal when a logic level of a mode signal is changed. The switching circuit receives a first clock signal, a second clock signal and an auxiliary clock signal. The switching circuit, based on the control signal, outputs one clock signal between the first clock signal and the second clock signal as a glitch free clock signal before the clock switch period, stops outputting the one clock signal and outputs the auxiliary clock signal as the glitch free clock signal during the clock switch period, and stops outputting the auxiliary clock signal and outputs another clock signal between the first clock signal and the second clock signal as the glitch free clock signal after the clock switch period.

Abstract: A clock switch device includes a controller and a switching circuit. The controller sets a clock switch period using a control signal when a logic level of a mode signal is changed. The switching circuit receives a first clock signal, a second clock signal and an auxiliary clock signal. The switching circuit, based on the control signal, outputs one clock signal between the first clock signal and the second clock signal as a glitch free clock signal before the clock switch period, stops outputting the one clock signal and outputs the auxiliary clock signal as the glitch free clock signal during the clock switch period, and stops outputting the auxiliary clock signal and outputs another clock signal between the first clock signal and the second clock signal as the glitch free clock signal after the clock switch period.

Abstract: A display interface system includes a display transmitter and a display receiver. The display transmitter transmits a control pattern having image type information about a type of an image to be displayed and selectively transmits image data according to the type of the image to be displayed. The display receiver receives the control pattern and selectively receives the image data based upon the image type information, reducing power consumption.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.

Abstract: A display interface system includes a display transmitter and a display receiver. The display transmitter transmits a control pattern having image type information about a type of an image to be displayed and selectively transmits image data according to the type of the image to be displayed. The display receiver receives the control pattern and selectively receives the image data based upon the image type information, reducing power consumption.

Abstract: A voltage-drop measuring circuit is capable of measuring a voltage-drop of a power supply voltage caused by a resistance component of a power line. The voltage-drop measuring circuit includes a sensing circuit and a voltage-drop detecting circuit. The sensing circuit includes a sensor configured to generate a sensing voltage received by the sensor from a power pad through a power line between the sensor and the power pad. The voltage-drop detecting circuit is arranged in a neighborhood of a power pad, and is configured to generate a reference voltage, compare the sensing voltage with the reference voltage to detect the voltage-drop, and generate a detecting signal in accordance with the voltage-drop.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.