Abstract: A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.

Abstract: Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

Abstract: A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.

Abstract: A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.

Abstract: A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer.

Abstract: Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

Abstract: Provided are FeRAM device constructions and fabrication methods that provide for the direct connection of metal patterns to ferroelectric capacitors. The FeRAM device constructions utilize a combination of one or more barrier layers incorporated in conductive plugs, barrier layers incorporated in primary conductive patterns or conductive patterns formed using one or more noble metals to suppress parametric drift associated with conventional FeRAM constructions.

Abstract: A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.

Abstract: A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.

Abstract: A memory device includes one or more layers of parallel strings of ferroelectric gate transistors on a substrate, each layer of parallel strings including a plurality of parallel line-shaped active regions and a plurality of word lines extending in parallel transversely across the active regions and disposed on ferroelectric patterns on the active regions. A string select gate line may extend transversely across the active regions in parallel with the word lines. A ground select gate line may extend transversely across the active regions in parallel with the word lines.

Abstract: Disclosed are methods of forming ferroelectric material layers introducing a plurality of metallorganic source compounds into the reaction chamber, the source compounds being supplied in an appropriate ratio for forming the ferroelectric material. These metallorganic source compounds are, in turn, reacted with a NyOx/O2 oxidant gas mixture in which the NyOxcomponent(s) represents at least 50 volume percent of the oxidant gas. This mixture of metallorganic source compounds and oxidant gas mixture(s) are maintained at a deposition temperature and deposition pressure within the reaction chamber suitable for causing a reaction between the metallorganic source compounds and the oxidant gas for a deposition period sufficient to form the ferroelectric material layer. The resulting ferroelectric material layers exhibit improved uniformity, for example, near the interface with the bottom electrode.

Abstract: In a ferroelectric structure after a first lower electrode film is formed using a first metal nitride, a second lower electrode film is formed on the first lower electrode film using a first metal, a second metal oxide and/or a first alloy. After a ferroelectric layer is formed on the second lower electrode film, a first upper electrode film is formed on the ferroelectric layer using a second alloy. Related devices are also disclosed.

Abstract: A ferroelectric capacitor structure can include a ferroelectric layer on a lower electrode and an upper electrode on the ferroelectric layer, the upper electrode including a metal oxide and a metal.