Abstract: A chip package includes a set of layers including conductive planes connected by vias. A first portion has at least one antenna, antenna ground plane, and first grounded vias. A second portion has a conductive plane parallel to the ground plane that forms an interface for connecting to at least one integrated circuit device. A third portion between the first and the second portion has a vertical transmission line that includes a signal via connecting the antenna feed line to the at least one integrated circuit and a parallel-plate mode suppression mechanism. The parallel-plate mode suppression mechanism includes a grounded reflector that forms a cage with the grounded vias around an antenna region and further includes second ground vias surrounding the signal via.

Abstract: A chip package includes a set of layers including conductive planes connected by vias. A first portion has at least one antenna, antenna ground plane, and first grounded vias. A second portion has a conductive plane parallel to the ground plane that forms an interface for connecting to at least one integrated circuit device. A third portion between the first and the second portion has a vertical transmission line that includes a signal via connecting the antenna feed line to the at least one integrated circuit and a parallel-plate mode suppression mechanism. The parallel-plate mode suppression mechanism includes a grounded reflector that forms a cage with the grounded vias around an antenna region and further includes second ground vias surrounding the signal via.

Abstract: A chip package includes a plurality of layers including conductive planes connected by vias. The layers include a first portion having an antenna formed therein and a parallel-plate mode suppression mechanism to suppress parallel-plate mode excitation of the antenna. The parallel-plate mode suppression mechanism includes a reflector offset from an antenna ground plane and first grounded vias. A second portion has an interface for connecting to an integrated circuit device wherein the first portion and the second portion are separated by the parallel-plate mode suppression mechanism.

Abstract: Array packages and methods for forming large-scale antenna arrays. One method includes aligning two or more array packages. The two or more array packages each include one or more bottom dielectric layers, an array of antennas arranged in a plane above the one or more bottom dielectric layers, a ground plane layer above the one or more bottom dielectric layers, and a conductive surface on at least a part of an outside surface of the array package and orthogonal to the plane of the array of antennas. The conductive surface is electrically connected to the ground plane layer.

Abstract: An apparatus, imager elements, and a method for detecting a radio frequency image using phased array techniques. An example apparatus includes an array of radio frequency antennas fabricated on one or more packaged integrated circuits. The apparatus also includes a controller configured to selectively phase shift radio frequency signals from the antennas such that the at least a portion of the radio frequency image is focused.

Abstract: Array packages and methods for forming large-scale antenna arrays. One method includes aligning two or more array packages. The two or more array packages each include one or more bottom dielectric layers, an array of antennas arranged in a plane above the one or more bottom dielectric layers, a ground plane layer above the one or more bottom dielectric layers, and a conductive surface on at least a part of an outside surface of the array package and orthogonal to the plane of the array of antennas. The conductive surface is electrically connected to the ground plane layer.

Abstract: A chip package includes a plurality of layers including conductive planes connected by vias. The layers include a first portion having an antenna formed therein and a parallel-plate mode suppression mechanism to suppress parallel-plate mode excitation of the antenna. The parallel-plate mode suppression mechanism includes a reflector offset from an antenna ground plane and first grounded vias. A second portion has an interface for connecting to an integrated circuit device wherein the first portion and the second portion are separated by the parallel-plate mode suppression mechanism.

Abstract: Techniques provide improved thermal interface material application in an assembly associated with an integrated circuit package. For example, an apparatus comprises an integrated circuit module, a printed circuit board, and a heat transfer device. The integrated circuit module is mounted on a first surface of the printed circuit board. The printed circuit board has at least one thermal interface material application via formed therein in alignment with the integrated circuit module. The heat transfer device is mounted on a second surface of the printed circuit board and is thermally coupled to the integrated circuit module. The second surface of the printed circuit board is opposite to the first surface of the printed circuit board.

Abstract: An apparatus, imager elements, and a method for detecting a radio frequency image using phased array techniques. An example apparatus includes an array of radio frequency antennas fabricated on one or more packaged integrated circuits. The apparatus also includes a controller configured to selectively phase shift radio frequency signals from the antennas such that the at least a portion of the radio frequency image is focused.