Patents by Inventor Donggeon Kim

Donggeon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135987
    Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.
    Type: Application
    Filed: June 22, 2023
    Publication date: April 25, 2024
    Inventors: DONGGEON KIM, BOK-YEON WON, SELYUNG YOON, JONGHYUK KIM
  • Patent number: 11922992
    Abstract: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inseok Baek, Bokyeon Won, Kyoungmin Kim, Donggeon Kim, Myeongsik Ryu, Sangwook Park, Seokjae Lee
  • Publication number: 20230365582
    Abstract: The present application relates to a novel compound having inhibitory activity on prostaglandin E2 receptor and uses thereof, and provides a compound represented by formula I, a solvate, stereoisomer or pharmaceutically acceptable salt thereof, a pharmaceutical composition comprising the same, and a method of using the same.
    Type: Application
    Filed: August 20, 2021
    Publication date: November 16, 2023
    Inventors: Young Sook SHIN, Sang Kyun LIM, Yeri LEE, Donggeon KIM, Soo Bong HAN, Chang Soo YUN, Hyun Jin KIM, Joo Youn LEE, Hyuk LEE, Sikwang SEONG
  • Patent number: 11818881
    Abstract: A sub word-line driver circuit of a semiconductor memory device includes a first active pattern and a second active pattern in a substrate, and a gate pattern. The first active pattern includes a first drain region and a first source region of a first keeping transistor that precharges a first word-line which is inactive and extends in a first direction with a negative voltage. The second active pattern includes a second drain region and a second source region of a second keeping transistor that precharges a second word-line which is inactive and extends in the first direction with the negative voltage. The gate pattern is on a portion of the first active pattern and on a portion of the second active pattern, partially overlaps the first active pattern and the second active pattern.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: November 14, 2023
    Inventors: Kyoungmin Kim, Donggeon Kim, Myeongsik Ryu, Sangwook Park, Inseok Baek, Bokyeon Won
  • Publication number: 20230295258
    Abstract: The present invention provides a bispecific antibody comprising IL-12 or a variant thereof and an antigen binding site that specifically binds to FAP. The bispecific antibody exhibits an anticancer effect by IL-12. In particular, when the anti-FAP antibody is implemented in one antibody, cancer may be efficiently treated by specifically targeting FAP expressed highly in a tumor, and specifically localizing IL-2 to the tumor site. Therefore, the bispecific antibody may be utilized as a pharmaceutical composition for anticancer treatment, and thus has high industrial application potential.
    Type: Application
    Filed: August 10, 2021
    Publication date: September 21, 2023
    Inventors: Donggeon KIM, Soomin RYU, Dahea LEE, Dongsu KIM, Jihoon CHANG, Byoung Chul LEE
  • Publication number: 20230295327
    Abstract: The present invention provides a bispecific antibody comprising IL-12 or a variant thereof and an antigen binding site that specifically binds to CD20. The bispecific antibody exhibits an anticancer effect by IL-12. In particular, when the anti-CD20 antibody is implemented in one antibody, IL-12 is specifically localized to a tumor site by targeting CD20, which is specifically expressed in a tumor at a high level, thereby efficiently treating cancer. Therefore, the bispecific antibody can be utilized as a pharmaceutical composition for anticancer treatment, and thus has a high potential for industrial application.
    Type: Application
    Filed: August 10, 2021
    Publication date: September 21, 2023
    Inventors: Dahea LEE, Soomin RYU, Donggeon KIM, Jihoon CHANG, Byoung Chul LEE
  • Patent number: 11735248
    Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: August 22, 2023
    Inventors: Seokjae Lee, Bok-Yeon Won, Kyoungmin Kim, Donggeon Kim, Myeongsik Ryu, Sangwook Park, Inseok Baek
  • Publication number: 20230258470
    Abstract: An electronic device is provided. The electronic device includes a global positioning system (GPS) module, a communication module, and a processor functionally connected to the GPS module and the communication module. The processor is configured to obtain second location information by refining the first location information, when the second location information is first sensitive information, filter the second location, and when the second location information is not the first sensitive information, convert the second location information into point-of-interest (POI) information on the basis of a mapping table, when the POI information is second sensitive information, filter the POI information, when the POI information is not the second sensitive information, transmit the POI information to an external electronic device through the communication module, and receive update information from the external electronic device in response to the transmission of the POI information.
    Type: Application
    Filed: April 26, 2023
    Publication date: August 17, 2023
    Inventors: Donggeon KIM, Hwangki MIN, Seungyeol YOO, Seokho YOON, Chungki LEE, Gajin SONG, Jaeyung YEO
  • Publication number: 20230242633
    Abstract: Provided is a fusion protein dimer containing an extracellular domain of CRIg or a fragment thereof, and a protein that specifically binds to VEGF. The protein may not only inhibit complement-related pathways, but also effectively modulate angiogenesis. Therefore, the fusion protein dimer may be effectively used for the treatment and prevention of complement-related diseases, specifically, eye diseases such as macular degeneration, and thus a high possibility of being industrially used.
    Type: Application
    Filed: July 7, 2021
    Publication date: August 3, 2023
    Inventors: Eu Ddeum CHUNG, Soomin RYU, Donggeon KIM, Jihoon CHANG, Byoung Chul LEE
  • Publication number: 20230232075
    Abstract: An electronic device may include a wireless communication circuit, a memory, and a processor. The memory may store instructions that allow, when executed, the processor to: obtain context information associated with the state of the electronic device, and contents information being provided by the electronic device; extracting first keywords on the basis of the context information and the contents information; analyze the keyword level for the first keywords; changing the first keywords into a superordinate concept according to preset keyword levels to obtain second keywords; and transmit the second keywords to at least one server by using the wireless communication circuit. Other various embodiments identified through the specification are possible.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 20, 2023
    Inventors: Hwangki MIN, Sungmin RHEE, Yuwon LEE, Donggeon KIM, Seungyeol YOO, Seokho YOON, Junyeop LEE, Chungki LEE, Gajin SONG, Jaeyung YEO
  • Publication number: 20230130345
    Abstract: A sub word-line driver circuit of a semiconductor memory device includes a first active pattern and a second active pattern in a substrate, and a gate pattern. The first active pattern includes a first drain region and a first source region of a first keeping transistor that precharges a first word-line which is inactive and extends in a first direction with a negative voltage. The second active pattern includes a second drain region and a second source region of a second keeping transistor that precharges a second word-line which is inactive and extends in the first direction with the negative voltage. The gate pattern is on a portion of the first active pattern and on a portion of the second active pattern, partially overlaps the first active pattern and the second active pattern.
    Type: Application
    Filed: March 31, 2022
    Publication date: April 27, 2023
    Inventors: KYOUNGMIN KIM, DONGGEON KIM, MYEONGSIK RYU, SANGWOOK PARK, INSEOK BAEK, BOKYEON WON
  • Publication number: 20230122198
    Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.
    Type: Application
    Filed: April 19, 2022
    Publication date: April 20, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Myeongsik RYU, Bokyeon WON, Kyoungmin KIM, Donggeon KIM, Sangwook PARK, Inseok BAEK
  • Publication number: 20220406360
    Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.
    Type: Application
    Filed: March 3, 2022
    Publication date: December 22, 2022
    Inventors: Seokjae Lee, Bok-Yeon Won, Kyoungmin Kim, Donggeon Kim, Myeongsik Ryu, Sangwook Park, Inseok Baek
  • Publication number: 20220406361
    Abstract: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.
    Type: Application
    Filed: May 31, 2022
    Publication date: December 22, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inseok Baek, Bokyeon Won, Kyoungmin Kim, Donggeon Kim, Myeongsik Ryu, Sangwook Park, Seokjae Lee
  • Patent number: 11349979
    Abstract: An electronic device according to an embodiment includes: a processor, and a memory configured to be operatively connected to the processor and to store a list including a plurality of profiles respectively corresponding to members recognized as users of the electronic device, wherein the memory stores, when executed, instructions that cause the processor to: acquire a usage pattern of the electronic device; compare a first profile used for configuring the electronic device among the plurality of profiles with the usage pattern; recognize a profile change based on a result of the comparison; retrieve a second profile matching the acquired usage pattern from the list based on the recognition of the profile change; and configure the electronic device using the second profile. In addition, various other embodiments are possible.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 31, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinho Mun, Mihwa Park, Donggeon Kim, Sungdeuk Park
  • Publication number: 20210136193
    Abstract: An electronic device according to an embodiment includes: a processor, and a memory configured to be operatively connected to the processor and to store a list including a plurality of profiles respectively corresponding to members recognized as users of the electronic device, wherein the memory stores, when executed, instructions that cause the processor to: acquire a usage pattern of the electronic device; compare a first profile used for configuring the electronic device among the plurality of profiles with the usage pattern; recognize a profile change based on a result of the comparison; retrieve a second profile matching the acquired usage pattern from the list based on the recognition of the profile change; and configure the electronic device using the second profile. In addition, various other embodiments are possible.
    Type: Application
    Filed: October 27, 2020
    Publication date: May 6, 2021
    Inventors: Jinho MUN, Mihwa PARK, Donggeon KIM, Sungdeuk PARK
  • Patent number: 5975861
    Abstract: A pumping assembly for use in ventilating footwear includes a supporting plate having a first protrusion which is formed in a center portion of an upper surface thereof; front and rear check valves which are respectively formed forwardly and rearwardly the first protrusion portion; an exhaust pipe which is connected to the front check valve; an intake pipe which is connected to the rear check valve; a spring which has a lower end inserted into the first protrusion on the supporting plate; a curve-shaped hard plate having a second protrusion portion which is formed in a center portion of a bottom surface thereof and is inserted into an upper end of the spring; and an elastic cover which has elasticity and tensibility and covers the hard plate. The cover is bonded to the hard plate, whereby the hard plate descends in such a manner that maximum volume variation within the elastic cover can occur; when the upper rear portion of a foot pressurizes the hard plate and the elastic cover is pressed down.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: November 2, 1999
    Inventors: Bongseop Shin, Donggeon Kim, Seonjoon Kim, Seongog Cho, Kwangseog Park