Abstract: A power-up signal generation circuit includes a discharge driving unit configured to discharge a voltage of a power-up detection node in response to a voltage of an external power supply voltage, a charge driving unit configured to charge the voltage of the power-up detection node in response to a voltage of an internal power supply voltage, a power reset discharging unit configured to discharge a voltage of the power-up detection node while the semiconductor integrated circuit is reset, and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node.

Abstract: A power-up signal generation circuit includes a main driving unit configured to drive a power-up detection node according to power supply voltage level information; an auxiliary driving unit configured to additionally drive the power-up detection node according to temperature information; and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node in accordance with the operations of the main driving unit and the auxiliary driving unit.

Abstract: A power-up signal generation circuit includes a discharge driving unit configured to discharge a voltage of a power-up detection node in response to a voltage of an external power supply voltage, a charge driving unit configured to charge the voltage of the power-up detection node in response to a voltage of an internal power supply voltage, a power reset discharging unit configured to discharge a voltage of the power-up detection node while the semiconductor integrated circuit is reset, and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node.

Abstract: A semiconductor integrated circuit includes a bump pad through which data is outputted, a probe test pad having a larger size than the bump pad, a first output drive unit configured to drive the bump pad at a first drivability in response to output data, a second output drive unit configured to drive the probe test pad at a second drivability higher than the first drivability in response to the output data, and a multiplexing unit configured to transfer the output data to the first output drive unit or the second output drive unit in response to a test mode signal.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A semiconductor integrated circuit includes a bump pad through which data is outputted, a probe test pad having a larger size than the bump pad, a first output drive unit configured to drive the bump pad at a first drivability in response to output data, a second output drive unit configured to drive the probe test pad at a second drivability higher than the first drivability in response to the output data, and a multiplexing unit configured to transfer the output data to the first output drive unit or the second output drive unit in response to a test mode signal.

Abstract: A power-up signal generation circuit includes a main driving unit configured to drive a power-up detection node according to power supply voltage level information; an auxiliary driving unit configured to additionally drive the power-up detection node according to temperature information; and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node in accordance with the operations of the main driving unit and the auxiliary driving unit.

Abstract: A semiconductor integrated circuit includes a first bump pad and a second bump pad configured to perform at least one of a data input operation and a data output operation in a normal mode; a probe pad configured to perform at least one of a data input operation and a data output operation in a test mode; a data output unit configured to communicate a data to one of the first bump pad and the probe pad; a data input unit configured to communicate a data from one of the second bump pad and the probe pad; a first switching unit configured to connect the probe pad and the data output unit in response to a test mode signal; and a second switching unit configured to connect the probe pad and the data input unit in response to the test mode signal.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.