Abstract: Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.

Abstract: The present disclosure relates to a liver organoid, more specifically, to a liver organoid in which a liver lobule-type structure can be maintained for a long time and a preparation method using the same. The liver organoid of the present disclosure comprises: a tubular outer cavity the inside of which is divided into a plurality of compartments; a cell aggregate loaded into the compartments; and an inner cavity located at the core of the outer cavity.

Abstract: Disclosed is a sealing member for a master cylinder. The sealing member for a master cylinder, which is formed in a ring shape and is installed between an inner surface of a cylinder body and an outer surface of a piston, includes an inner wing part configured to contact the outer surface of the piston, an outer wing part configured to contact the inner surface of the cylinder body, and a sealing rear wall part configured to connect the inner wing part and the outer wing part. The sealing rear wall part is provided with an oil passage to connect an oil entrance formed at the inner wing part and an oil entrance formed at the outer wing part, and the oil passage includes a retardation passage which is longer than a shortest straight-line distance which directly connects the oil entrances.

Abstract: Disclosed is a sealing member for a master cylinder. The sealing member for a master cylinder, which is formed in a ring shape and is installed between an inner surface of a cylinder body and an outer surface of a piston, includes an inner wing part configured to contact the outer surface of the piston, an outer wing part configured to contact the inner surface of the cylinder body, and a sealing rear wall part configured to connect the inner wing part and the outer wing part. The sealing rear wall part is provided with an oil passage to connect an oil entrance formed at the inner wing part and an oil entrance formed at the outer wing part, and the oil passage includes a retardation passage which is longer than a shortest straight-line distance which directly connects the oil entrances.

Abstract: A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently.

Abstract: Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

Abstract: Disclosed is a sealing member for a master cylinder and the master cylinder having the same, capable of shortening the delay in the release operation of the hill start assist control system. The sealing member includes an outer blade making contact with the cylinder body and an inner blade making contact with the outer surface of the piston. The inner blade includes a circumferential fluid path extending in a circumferential direction of the inner blade and a plurality of axial fluid paths connected to the circumferential fluid path.

Abstract: Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

Abstract: Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

Abstract: A memory system having a flash memory device that performs an over-sampling read operation to read data from a memory cell in the flash device by using an over-sampling read voltage that falls within a threshold voltage distribution range. A memory controller supplies a read mode signal to the flash memory device to perform the over-sampling read operation.

Abstract: A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently.

Abstract: Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

Abstract: A memory system having a flash memory device that performs an over-sampling read operation to read data from a memory cell in the flash device by using an over-sampling read voltage that falls within a threshold voltage distribution range. A memory controller supplies a read mode signal to the flash memory device to perform the over-sampling read operation.