Abstract: A semiconductor device includes a first gate isolation structure. A second gate isolation structure is spaced apart from the first gate isolation structure in a first direction. A first active pattern is disposed between the first and second gate isolation structures. The first active pattern extends longitudinally in a second direction crossing the first direction. A second active pattern is disposed between the first and second gate isolation structures. The second active pattern extends longitudinally in the second direction and is spaced apart from the first active pattern in the first direction. Gate structures are disposed between the first and second gate isolation structures. The gate structures directly contact the first and second gate isolation structures. A length of the first gate isolation structure in the second direction is greater than a length of the second gate isolation structure in the second direction.

Abstract: A semiconductor device and a method of manufacturing the same are provided. A semiconductor device includes: an active pattern including a lower pattern and a plurality of sheet patterns spaced apart from each other on the lower pattern; a gate structure positioned on the lower pattern and surrounding the sheet patterns; source/drain patterns positioned on both sides of the gate structure, and stacked patterns positioned between the source/drain patterns and the sheet patterns, wherein a stacked pattern includes a first stacked pattern and a second stacked pattern sequentially stacked on a side surface of a sheet pattern, the second stacked pattern including a material different from a material of the first stacked pattern, and a first width of the sheet pattern is smaller than a second width of the gate structure.

Abstract: A semiconductor device includes an active pattern with a first impurity having a first conductivity, first and second nanosheets on the active pattern, a gate electrode on the active pattern and surrounding each of the first and second nanosheets, a lower source/drain region on the active pattern, an uppermost surface of the lower source/drain region being lower than a lower surface of the second nanosheet, and the lower source/drain region being doped with a second impurity having the first conductivity, an upper source/drain region on the lower source/drain region, the upper source/drain region being doped with a third impurity having a second conductivity different from the first conductivity, and a gate insulation layer between the gate electrode and the lower and upper source/drain regions, the gate insulation layer being in contact with each of the lower and upper source/drain regions.

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.

Abstract: A simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, imaging generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors (EDF) respectively for the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating first to m-th epitaxy times for first to m-th effective open silicon densities.

Abstract: A simulation method and system which can determine a predictable epitaxy time by accurately reflecting layout characteristics of a chip and characteristics of a source/drain formation process are provided.