Abstract: A semiconductor device for a test mode setup is disclosed, which allows an SDRAM user to prevent an unwanted test mode from being set up. The semiconductor device for a test mode setup includes a command decoder for outputting a first address signal through a plurality of input signals, a shift register for outputting a second address signal, a logic part for outputting a test register setup signal by combining the first address signal with the second address signal, a test register for storing the test register setup signal, and a test decoder for outputting a test mode signal in response to the test register setup signal stored in the test register.

Abstract: A circuit for generating a switching control signal which is capable of selectively connecting an internal voltage in the read mode with respect to the driving voltage of a driver and connecting an external voltage in the write mode. The circuit includes a Y-decoder for decoding a Y-address, a Y-driver driven by an internal voltage or an external voltage for outputting a switching control signal, a first switching means controlled by a read enabling bar signal and applying or blocking the internal voltage to/from the Y-driver, and a second switching means controlled by the write enabling signal for applying or blocking the external voltage to/from the Y-driver.

Abstract: Data-outputting buffer circuit suitable for reducing noise which is generated in an output buffer circuit part when minus electric filed is applied to a data output pad in inputting data is disclosed, including a noise generation restraining part detecting a level of a signal applied to an input/output pad inputting and outputting data for outputting first and second noise generation restraining signals, a pullup transistor having a source connected to the input/output pad and a drain electrode connected to a power voltage terminal, a pulldown transistor serially connected to the pullup transistor with both sources of the pullup and pulldown transistors connected to the input/output pad, first and second driving parts for driving the pullup transistor and the pulldown transistor, and a clamp transistor turned on by the first noise generation restraining signal for restraining increase of substrate bias due to voltage difference between a gate and the source of the pullup transistor.

Abstract: An parallel test circuit for memory device is provided. The parallel test circuit according to the present invention includes: a plurality of memory mats, wherein each of memory mats comprises a memory cell for writing two-bit data and an X, Y address decoder for accessing the memory cell; a amplifying unit having a plurality of main amplifiers, wherein each of main amplifiers compares and amplifies a voltage difference between two-bit data of corresponding memory cell, and thereby output one-bit logic value; a data reducing unit for reducing a plurality of logic value from the amplifying unit to one-bit logic value. Accordingly, the parallel test circuit according to the present invention improves test efficiency twice by which a single main amplifier compares and amplifies two-bit data.

Abstract: A sensing circuit, in which a semidirect system is used for simplifying a circuit system, is disclosed. The sensing circuit includes: a data bus having a data line and a data bar line for reading operations and/or writing operations; a first transistor for controlling an indirect read operation; a second and third transistor, connected to the data lines, respectively, each also being connected to the same end of said first transistor, for selectively connecting one of the data lines to the first transistor; and a fourth transistor and a fifth transistor for selectively connecting the data bus to the bit line and the bit bar line, respectively, to control a direct writing operation.