Patents by Inventor Dong Gyu EO

Dong Gyu EO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11616086
    Abstract: A thin film transistor panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate and including a first semiconductor layer including a low temperature polysilicon and a first control electrode overlapping the first semiconductor layer; a second transistor disposed on the substrate and including a second semiconductor layer including an oxide semiconductor and a second control electrode overlapping the second semiconductor layer; a first gate insulation layer disposed between the first semiconductor layer and the first control electrode of the first transistor and including a first insulation layer and a second insulation layer; and a second gate insulation layer disposed between the second semiconductor layer and the second control electrode of the second transistor and including the second insulation layer, wherein the density of the first insulation layer may be higher than the density of the second insulation layer, the first semiconductor layer of the f
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: March 28, 2023
    Assignee: ADRC. CO. KR
    Inventors: Duk Young Jeong, Chae Yeon Hwang, Dong Gyu Eo
  • Publication number: 20210210525
    Abstract: A thin film transistor panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate and including a first semiconductor layer including a low temperature polysilicon and a first control electrode overlapping the first semiconductor layer; a second transistor disposed on the substrate and including a second semiconductor layer including an oxide semiconductor and a second control electrode overlapping the second semiconductor layer; a first gate insulation layer disposed between the first semiconductor layer and the first control electrode of the first transistor and including a first insulation layer and a second insulation layer; and a second gate insulation layer disposed between the second semiconductor layer and the second control electrode of the second transistor and including the second insulation layer, wherein the density of the first insulation layer may be higher than the density of the second insulation layer, the first semiconductor layer of the f
    Type: Application
    Filed: December 17, 2020
    Publication date: July 8, 2021
    Inventors: Duk Young JEONG, Chae Yeon HWANG, Dong Gyu EO