Abstract: A chip information output circuit including a fuse box, capable of reducing a layout area without affecting input capacitance, is provided. The chip information output circuit includes a plurality of fuse blocks for generating different outputs according to whether a fuse is cut and a pipeline circuit for receiving a plurality of signals, which are output in parallel from the respective fuse blocks, and serially outputting the plurality of signals. Each of the fuse blocks includes a plurality of fuse boxes for generating output signals, the levels of which are either a high or low logic level according to whether the fuses included therein are cut, wherein the respective fuse boxes are enabled in response to the respective control signals and the output lines of the fuse boxes are wired by an OR operation. The pipeline circuit includes a plurality of serially connected latch units for latching signals output from the fuse blocks and outputting the latched signals.