Abstract: A display device includes a first substrate and a second substrate facing each other; and a filling layer disposed between the first substrate and the second substrate. The first substrate comprises a support substrate comprising a display area in which emission areas associated with sub-pixels, are arranged; a light-emitting element layer disposed on one surface of the support substrate; and an encapsulation layer disposed on the light-emitting element layer. The encapsulation layer comprises a first inorganic layer covering the light-emitting element layer; an organic layer disposed on the first inorganic layer and overlapping the light-emitting element layer; and a second inorganic layer disposed on the first inorganic layer and covering the organic layer. A thickness of the first inorganic layer is smaller than a thickness of the second inorganic layer.

Abstract: A data storage device may include a storage configured to receive and program data in units of first sizes or read and output data in the units of first sizes and a memory controller. The memory controller is configured to generate a mapping information slice having a first size as a trim command including a first logical address which is transmitted thereto from an external device, the mapping information slice including trim bitmap data and first mapping data for the first logical address, and store the mapping information slice in the storage.

Abstract: The present technology relates to an electronic device. A storage device includes a memory device including pages, a buffer memory configured to store address mapping information including a mapping relationship between logical addresses provided from a host and physical addresses corresponding to the pages, first trim bitmap information including trim information of first logical address groups each including a first number of logical addresses having at least two of the logical addresses, and second trim bitmap information including trim information of second logical address groups each including a second number of logical addresses greater than the first number of the logical addresses, and a memory controller configured to change, based on a number of trim-requested logical addresses from the host, map states of the trim-requested logical addresses in one of the address mapping information, the first trim bitmap information, and the second trim bitmap information.

Abstract: A memory system, a memory controller and an operating method are disclosed. When a target command which instructs an operation of writing target data to a memory device is received from a host, the target data is divided into data units, and a first data unit among the data units is controlled such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. As a consequence, it is possible to write data in specific units in a memory system using a multi-core.

Abstract: A storage device includes a semiconductor memory device including memory blocks, planes which include the memory blocks and memory dies in which the planes are included; and a controller configured to store user data and metadata determined based on a command received from a host, in super memory blocks each including some of the memory blocks. The controller includes a segment queuing circuit configured to queue segments of the user data or the metadata to N (N is a natural number) virtual die queues according to a striping scheme; and a segment storage circuit configured to store the queued segments of the user data or the metadata in a super memory block among the super memory blocks, wherein the queued segments of the user data or the metadata are stored in the memory blocks included in the super memory block, according to a striping scheme.

Abstract: The present technology relates to an electronic device. A storage device includes a memory device including pages, a buffer memory configured to store address mapping information including a mapping relationship between logical addresses provided from a host and physical addresses corresponding to the pages, first trim bitmap information including trim information of first logical address groups each including a first number of logical addresses having at least two of the logical addresses, and second trim bitmap information including trim information of second logical address groups each including a second number of logical addresses greater than the first number of the logical addresses, and a memory controller configured to change, based on a number of trim-requested logical addresses from the host, map states of the trim-requested logical addresses in one of the address mapping information, the first trim bitmap information, and the second trim bitmap information.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method. The present disclosure may divide user data and map data corresponding to the user data into data segments, may input the data segments in N virtual die queues, and may program the same in a memory device, wherein a user data segment input in the virtual die queue is programmed according to two program schemes, thereby quickly programming the user data and the map data in the memory device and quickly updating the map data in a map cache.

Abstract: A memory system includes a memory controller. The memory controller includes: a buffer memory configured to store read count values of memory blocks and address mapping information of the memory blocks; and a central processing unit configured to monitor the read count values, and determine whether a refresh operation of target blocks, among the memory blocks, is to be performed on all memory blocks including target blocks in a super block, in a unit of the super block or on the target memory blocks in the super block in a unit of a single block, based on the monitoring result.

Abstract: A memory system, a memory controller and an operating method are disclosed. When a target command which instructs an operation of writing target data to a memory device is received from a host, the target data is divided into data units, and a first data unit among the data units is controlled such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. As a consequence, it is possible to write data in specific units in a memory system using a multi-core.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method. The present disclosure may divide user data and map data corresponding to the user data into data segments, may input the data segments in N virtual die queues, and may program the same in a memory device, wherein a user data segment input in the virtual die queue is programmed according to two program schemes, thereby quickly programming the user data and the map data in the memory device and quickly updating the map data in a map cache.

Abstract: A storage device includes a semiconductor memory device including memory blocks, planes which include the memory blocks and memory dies in which the planes are included; and a controller configured to store user data and metadata determined based on a command received from a host, in super memory blocks each including some of the memory blocks. The controller includes a segment queuing circuit configured to queue segments of the user data or the metadata to N (N is a natural number) virtual die queues according to a striping scheme; and a segment storage circuit configured to store the queued segments of the user data or the metadata in a super memory block among the super memory blocks, wherein the queued segments of the user data or the metadata are stored in the memory blocks included in the super memory block, according to a striping scheme.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include: a memory device including a plurality of memory blocks; and a controller configured to generate one or more streams in response to a request from a host, configure one or more super blocks respectively corresponding to the one or more streams, each of the one or more super blocks including free blocks, and control the memory device to perform a data write operation on the one or more super blocks. The controller may allocate, among the one or more super blocks, an additional free block to a super block that needs the additional free block when the data write operation has not yet been completed.

Abstract: The present disclosure relates to a memory system and an operating method thereof. The memory system includes a memory device including a plurality of memory blocks; and a controller configuring a plurality of super blocks by grouping the plurality of memory blocks and controlling overall operations of each of the plurality of super blocks, wherein the controller performs wear leveling on the basis of first erase counts, one for each of the plurality of super blocks, and wherein the controller performs wear leveling on the basis of second erase counts, one for each of memory blocks in a super block in which a memory block becomes a bad block, among the plurality of super blocks.

Abstract: A memory system includes a memory controller. The memory controller includes: a buffer memory configured to store read count values of memory blocks and address mapping information of the memory blocks; and a central processing unit configured to monitor the read count values, and determine whether a refresh operation of target blocks, among the memory blocks, is to be performed on all memory blocks including target blocks in a super block, in a unit of the super block or on the target memory blocks in the super block in a unit of a single block, based on the monitoring result.

Abstract: The present invention relates to a method and apparatus for analyzing functionality and test paths of product line using a priority graph. The apparatus includes: a parser for analyzing a use case scenario expressed in a text format, in a unit of word to separate a word from the analyzed use case scenario; an object/behavior identifier for extracting core noun and verb from the separated word; a dependency graph modeler for supporting to model an execution flow of a function; a priority graph editor for supporting to analyze and express linked feature objects, a feature category, a default value, a reference value, a use case name, variation points; a test path identifier for identifying a test path to examine requirements and plan a test at an information expression of a priority graph; and a graphic information processor for visually changing and showing an analysis information of the dependency graph and the priority graph.