Abstract: The present disclosure relates to a CPU module for processing railway signals. The CPU module includes a first input unit that receives an input signal from an external apparatus; a second input unit that receives a second input signal and a second instruction signal from a CPU checking module; a first comparison unit that compares the two input signals and outputs a resulting input signal if it is determined that the two signals are identical; a signal processing unit that converts the resulting input signal into a first instruction signal; and a second comparison unit that compares the first instruction signal with the second instruction signal and outputs a resulting instruction signal if it determines the two instruction signals are identical; and a control unit that sends a synchronization signal for controlling operation timing of the two comparison units, the signal processing unit, and the CPU checking module.

Abstract: The present disclosure relates to a CPU module for processing railway signals, and more specifically to a CPU module for processing railway signals that controls operation timing of a first comparator, a signal processing unit and a second comparator.