Patents by Inventor Dong-Ho Cha

Dong-Ho Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363120
    Abstract: A method for transmitting voice data is provided. The method may include receiving voice data of a particular speaker from a voice data collection server; determining whether destination terminals are first-type terminals; and based on a determination that the destination terminals are the first-type terminals, transmitting the received voice data to the destination terminals through a channel corresponding to the particular speaker, from among a plurality of predefined channels for the destination terminals.
    Type: Application
    Filed: January 5, 2024
    Publication date: October 31, 2024
    Applicant: SAMSUNG SDS CO., LTD.
    Inventors: Jung Ho KIM, Young Kwang KIM, Soo Hwan PARK, Sang Wook LEE, Dong Ho CHA, Jun Ho KANG, Hee Tae YOON
  • Publication number: 20240258077
    Abstract: The present invention relates to a technology for increasing the reliability of measurement by preventing the contamination of a self-plasma chamber provided in order to monitor a deposition operation performed in a process chamber, and has a shielding means capable of preventing an inflow of negative electrode material, which is generated by a sputtering phenomenon, into a discharge chamber when a positive charge of plasma, which is generated in the self-plasma chamber, collides with a negative electrode.
    Type: Application
    Filed: April 12, 2024
    Publication date: August 1, 2024
    Applicant: NANOTECH INC.
    Inventor: Dong Ho CHA
  • Patent number: 11990320
    Abstract: The present invention relates to a technology for increasing the reliability of measurement by preventing the contamination of a self-plasma chamber provided in order to monitor a deposition operation performed in a process chamber, and has a shielding means capable of preventing an inflow of negative electrode material, which is generated by a sputtering phenomenon, into a discharge chamber when a positive charge of plasma, which is generated in the self-plasma chamber, collides with a negative electrode.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 21, 2024
    Assignee: NANOTECH INC.
    Inventor: Dong Ho Cha
  • Patent number: 11876019
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Publication number: 20220301939
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Publication number: 20220068718
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Patent number: 11201086
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 14, 2021
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Publication number: 20200273676
    Abstract: The present invention relates to a technology for increasing the reliability of measurement by preventing the contamination of a self-plasma chamber provided in order to monitor a deposition operation performed in a process chamber, and has a shielding means capable of preventing an inflow of negative electrode material, which is generated by a sputtering phenomenon, into a discharge chamber when a positive charge of plasma, which is generated in the self-plasma chamber, collides with a negative electrode.
    Type: Application
    Filed: August 7, 2018
    Publication date: August 27, 2020
    Applicant: NANOTECH INC.
    Inventor: Dong Ho Cha
  • Publication number: 20200227321
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Patent number: 10643898
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Patent number: 10483399
    Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-yup Chung, Myung-yoon Um, Dong-ho Cha, Jung-gun You, Gi-gwan Park
  • Patent number: 10403754
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Publication number: 20190051566
    Abstract: A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Inventors: Sung-Min Kim, Ji-Su Kang, Byung-Chan Ryu, Jae-Hyun Park, Yu-Ri Lee, Dong-Ho Cha
  • Patent number: 10199499
    Abstract: A semiconductor device includes first through fourth active fins, which extend alongside one another in a first direction; and a field insulating film that covers lower portions of the first through fourth active fins, the first and second active fins protrude from the field insulating film at a first height, the third active fin protrudes from the field insulating film at a second height different from the first height, and an interval between the first and second active fins is different from an interval between the third and fourth active fins.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Dong-Ho Cha, Sunhom Steve Paak
  • Publication number: 20190035934
    Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 31, 2019
    Inventors: Jae-yup CHUNG, Myung-yoon UM, Dong-ho CHA, Jung-gun YOU, Gi-gwan PARK
  • Patent number: 10147650
    Abstract: A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: December 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Ji-Su Kang, Byung-Chan Ryu, Jae-Hyun Park, Yu-Ri Lee, Dong-Ho Cha
  • Patent number: 10096714
    Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-yup Chung, Myung-yoon Um, Dong-ho Cha, Jung-gun You, Gi-gwan Park
  • Publication number: 20180254341
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Application
    Filed: May 3, 2018
    Publication date: September 6, 2018
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Publication number: 20180190543
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: February 23, 2018
    Publication date: July 5, 2018
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Patent number: 9991387
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha