Abstract: A display driver circuit, including a source driver configured to drive source lines of a display panel, and a timing controller configured to transfer image data to the source driver and to control the source driver such that the transferred image data is displayed via the display panel, the timing controller also being configured to transfer to the source driver a control signal and a test pattern, which are used to test a bit error rate, and the source driver being configured to test the bit error rate of the transferred test pattern in response to the transferred control signal.

Abstract: The display driving circuit including a type detector for receiving a data packet including a 2-bit embedded signal, in which a clock signal embedded in a data signal, and outputting a first reference clock or a second reference clock different from the first reference clock according to a type of the data packet, a window generator for receiving multi-phase clocks and providing to the type detector a first window reference and a second window reference different from the first window reference to be used in determining the type of the data packet, a buffer for delaying the first reference clock by a first interval and delaying the second reference clock by a second interval different from the first interval, and a multiplexer for multiplexing the delayed first and second reference clocks and outputting a multiplexed reference clock may be provided.

Abstract: According to an example embodiment, a display driving integrated circuit (IC) includes a timing controller and a plurality of source drivers. The timing controller is configured to output a plurality of signals to the plurality of source drivers, and at least one of the timing controller and the plurality of source drivers operates in a power down mode in at least one of an initializing period, a data transmission period, and a vertical blank period. According to an example embodiment, a mode conversion method used in a display driving IC includes switching between a normal mode to a power down mode in response to a standby control signal. The power down mode is implemented on at least one of a timing controller and a plurality of source drivers included in the display driving IC in at least one of an initializing period, a data transmission period, and a vertical blank period.

Abstract: A timing controller, a source driver, and a display driver integrated circuit (DDI) having improved test efficiency and a method of operating the DDI are provided. The timing controller includes a code generation unit for generating a first code from display data, a protocol encoder for generating a data sequence including the display data and the first code, and a transmission unit for providing the data sequence to a source driver through a link.

Abstract: Display driver circuits include a multi-function driver, which is configured to support first and second modes of operation. The multi-function driver supports the first mode of operation in response to a first control signal by driving a bus with an output signal, which has a value that indicates a locked or unlocked status of a clock signal therein. The multi-function driver also supports the second mode of operation in response to a second control signal by driving the bus with multi-bit data that is unrelated to the locked or unlocked status of the clock signal.

Abstract: A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.

Abstract: A display driver circuit includes a source driver and a display driver. The source driver drives source lines of a display panel, and the timing controller transmits image data to the source driver and controls the source driver such that the transmitted image data is displayed in the display panel. The timing controller randomizes the image data in a scrambling mode when the timing controller transmits data packets including pixel data field in which the image data is written.

Abstract: A system for transmitting and receiving a signal includes a transmitter that switches a first reference voltage and a second reference voltage and generates first and second voltage signals, and a receiver the receives the first and second voltage signals. The transmitter includes a reference voltage generator that generates the first reference voltage and the second reference voltage, and a switch block that switches the first reference voltage and the second reference voltage and outputs the first and second voltage signals. The receiver includes a resistor having two terminals to which the first and second voltage signals are applied.

Abstract: A method of transferring data between a timing controller and a plurality of source drivers in a display device is disclosed. The method includes: (a) setting a first source driver of the plurality of source drivers to convert first signals having first voltage levels to second signals having second voltage levels; (b) receiving, by the first source driver, a first test pattern from the timing controller; (c) performing a test by the first source driver, based on the first test pattern, to determine whether an error has occurred in the first test pattern; and (d) when an error has occurred in the first test pattern, adjusting, by the first source driver, an output level of a receiver of the first source driver, so that the first source driver converts the first signals to third signals having third voltage levels different from the second voltage levels.

Abstract: Display driver circuits include a multi-function driver, which is configured to support first and second modes of operation. The multi-function driver supports the first mode of operation in response to a first control signal by driving a bus with an output signal, which has a value that indicates a locked or unlocked status of a clock signal therein. The multi-function driver also supports the second mode of operation in response to a second control signal by driving the bus with multi-bit data that is unrelated to the locked or unlocked status of the clock signal.

Abstract: A method and apparatus for driving a display panel in which a bus link between a timing controller and a source driver block is altered in order to simplify the structure of a circuit. The apparatus includes a timing controller to generate signals including data and a reference signal for driving the display panel at a display driving time. A plurality of source drivers generate signals for driving data lines of the display panel using the signals generated by the timing controller. First signal transmission means are provided for transmitting the data from the timing controller to each of the plurality of source drivers using a point-to-point connection link, and a bus for transmitting the reference signal generated by the timing controller to one of the plurality of source drivers. Also, second signal transmission means are provided for transmitting the reference signal between the plurality of source drivers using a serial cascade connection link.

Abstract: A display driver circuit, including a source driver configured to drive source lines of a display panel, and a timing controller configured to transfer image data to the source driver and to control the source driver such that the transferred image data is displayed via the display panel, the timing controller also being configured to transfer to the source driver a control signal and a test pattern, which are used to test a bit error rate, and the source driver being configured to test the bit error rate of the transferred test pattern in response to the transferred control signal.

Abstract: According to an example embodiment, a display driving integrated circuit (IC) includes a timing controller and a plurality of source drivers. The timing controller is configured to output a plurality of signals to the plurality of source drivers, and at least one of the timing controller and the plurality of source drivers operates in a power down mode in at least one of an initializing period, a data transmission period, and a vertical blank period. According to an example embodiment, a mode conversion method used in a display driving IC includes switching between a normal mode to a power down mode in response to a standby control signal. The power down mode is implemented on at least one of a timing controller and a plurality of source drivers included in the display driving IC in at least one of an initializing period, a data transmission period, and a vertical blank period.

Abstract: A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.

Abstract: A system for transmitting and receiving a signal includes a transmitter that switches a first reference voltage and a second reference voltage and generates first and second voltage signals, and a receiver the receives the first and second voltage signals. The transmitter includes a reference voltage generator that generates the first reference voltage and the second reference voltage, and a switch block that switches the first reference voltage and the second reference voltage and outputs the first and second voltage signals. The receiver includes a resistor having two terminals to which the first and second voltage signals are applied.

Abstract: An interface method for a data transmitting and receiving system including a transmitter and a receiver includes; resetting the receiver in response to a data stream communicated from the transmitter or upon detecting power-up of the transmitter or receiver, and operating the receiver in response to a current data stream received from the transmitter, wherein the operating of the receiver comprises at least one of; (a) updating data stored in the receiver according to control data contained in the current data stream, and (b) receiving payload data contained in the current data stream.

Abstract: Embodiments of methods and apparatus for receiving data are disclosed. More particularly, methods of receiving a current mode signal, which can improve a signal to noise ratio (SNR) according to a change in a power supply voltage, and current mode comparators and semiconductor devices that use the methods are provided. A method of receiving a current mode signal includes receiving a reference current signal and a data current signal through a channel and generating a sensing voltage based on a difference between the reference current signal and the data current signal, varying a transconductance to reduce an input resistance of the current mode comparator in inverse proportion to an increase in a power supply voltage supplied to the current mode comparator, and converting the sensing voltage into a CMOS level output signal using the current mode comparator.

Abstract: A method and apparatus for driving a display panel in which a bus link between a timing controller and a source driver block is altered in order to simplify the structure of a circuit. The apparatus includes a timing controller to generate signals including data and a reference signal for driving the display panel at a display driving time. A plurality of source drivers generate signals for driving data lines of the display panel using the signals generated by the timing controller. First signal transmission means are provided for transmitting the data from the timing controller to each of the plurality of source drivers using a point-to-point connection link, and a bus for transmitting the reference signal generated by the timing controller to one of the plurality of source drivers. Also, second signal transmission means are provided for transmitting the reference signal between the plurality of source drivers using a serial cascade connection link.

Abstract: Embodiments of methods and apparatus for receiving data are disclosed. More particularly, methods of receiving a current mode signal, which can improve a signal to noise ratio (SNR) according to a change in a power supply voltage, and current mode comparators and semiconductor devices that use the methods are provided. A method of receiving a current mode signal includes receiving a reference current signal and a data current signal through a channel and generating a sensing voltage based on a difference between the reference current signal and the data current signal, varying a transconductance to reduce an input resistance of the current mode comparator in inverse proportion to an increase in a power supply voltage supplied to the current mode comparator, and converting the sensing voltage into a CMOS level output signal using the current mode comparator.