Patents by Inventor Dong Hwan JIN

Dong Hwan JIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Analog-to-digital converter (ADC) with reset skipping operation and analog-to-digital conversion method
    Patent number: 10680636
    Abstract: An analog-to-digital converter (ADC) is provided. The ADC may include an input terminal configured to receive input signals, a digital-to-analog converter (DAC), a first switch configured to control a connection between the DAC and the input terminal, a comparator, a second switch configured to control a connection between the DAC and the comparator, and a controller configured to control the first switch, the second switch, the DAC and the comparator.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 9, 2020
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: JongPal Kim, Ye Dam Kim, Seung Tak Ryu, Min Jae Seo, Dong Hwan Jin
  • ANALOG-TO-DIGITAL CONVERTER (ADC) WITH RESET SKIPPING OPERATION AND ANALOG-TO-DIGITAL CONVERSION METHOD
    Publication number: 20190296760
    Abstract: An analog-to-digital converter (ADC) is provided. The ADC comprises an input terminal configured to receive input signals, a digital-to-analog converter (DAC), a first switch configured to control a connection between the DAC and the input terminal, a comparator, a second switch configured to control a connection between the DAC and the comparator, and a controller configured to control the first switch, the second switch, the DAC and the comparator.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 26, 2019
    Applicants: SAMSUNG ELECTRONICS CO., LTD., Korea Advanced Institute of Science and Technology
    Inventors: JongPal KIM, Ye Dam KIM, Seung Tak RYU, Min Jae SEO, Dong Hwan JIN
  • MULTI-LEVEL MEMORY APPARATUS AND DATA SENSING METHOD THEREOF
    Publication number: 20160118115
    Abstract: A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.
    Type: Application
    Filed: June 22, 2015
    Publication date: April 28, 2016
    Inventors: Seung Tak RYU, Ji Wook KWON, Dong Hwan JIN
  • Multi-level memory apparatus and data sensing method thereof
    Patent number: 9318195
    Abstract: A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 19, 2016
    Assignees: SK HYNIX INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Seung Tak Ryu, Ji Wook Kwon, Dong Hwan Jin
  • Multi-level memory apparatus and data sensing method thereof
    Patent number: 9159411
    Abstract: A multi-level memory apparatus includes two or more current paths configured to pass currents having different levels, a memory cell selectively coupled to the two or more current paths, and a cell current copy unit configured to copy a cell current flowing through the memory cell.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: October 13, 2015
    Assignees: SK Hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Chul Hyun Park, Seung Tak Ryu, Ji Wook Kwon, Dong Hwan Jin
  • MULTI-LEVEL MEMORY APPARATUS AND DATA SENSING METHOD THEREOF
    Publication number: 20140010023
    Abstract: A multi-level memory apparatus includes two or more current paths configured to pass currents having different levels, a memory cell selectively coupled to the two or more current paths, and a cell current copy unit configured to copy a cell current flowing through the memory cell.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 9, 2014
    Inventors: Chul Hyun PARK, Seung Tak RYU, Ji Wook KWON, Dong Hwan JIN