Patents by Inventor Dong-Hyeon Ki

Dong-Hyeon Ki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060177770
    Abstract: The present invention relates to a thin film transistor (TFT) substrate and method of making such a TFT substrate. The structure of the TFT substrate helps prevent damage to signal lines in non-display areas.
    Type: Application
    Filed: December 15, 2005
    Publication date: August 10, 2006
    Inventors: Jeong-il Kim, Dong-hyeon Ki, Yun-hee Kwak, Hyeong-jun Park, Byeong-jae Ahn, Shin-tack Kang
  • Publication number: 20060157705
    Abstract: A thin film transistor array panel is provided, comprising: a gate line on an insulating substrate; a storage electrode line on the insulating substrate; a gate insulating layer over the gate line and the storage electrode line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode on the semiconductor layer and separated from each other; a lower passivation layer formed on the semiconductor layer and having a first contact hole exposing the drain electrode; a color filter on the lower passivation layer; an upper passivation layer on the color filter and having a second contact hole exposing the drain electrode; and a pixel electrode connected to the drain electrode through the first and second contact holes; wherein the storage electrode line has a light blocking member parallel to the data line.
    Type: Application
    Filed: January 4, 2006
    Publication date: July 20, 2006
    Inventor: Dong-Hyeon Ki
  • Publication number: 20050208711
    Abstract: A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside.
    Type: Application
    Filed: May 11, 2005
    Publication date: September 22, 2005
    Inventors: Woon-Yong Park, Hyeon-Hwan Kim, Dong-Hyeon Ki
  • Patent number: 6906776
    Abstract: A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: June 14, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woon-Yong Park, Hyeon-Hwan Kim, Dong-Hyeon Ki
  • Patent number: 6876405
    Abstract: A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: April 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woon-Yong Park, Hyeon-Hwan Kim, Dong-Hyeon Ki
  • Publication number: 20040239826
    Abstract: A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside.
    Type: Application
    Filed: July 25, 2003
    Publication date: December 2, 2004
    Inventors: Woon-Yong Park, Hyeon-Hwan Kim, Dong-Hyeon Ki
  • Patent number: 6678018
    Abstract: A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: January 13, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woon-Yong Park, Hyeon-Hwan Kim, Dong-Hyeon Ki
  • Publication number: 20020057393
    Abstract: A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside.
    Type: Application
    Filed: February 9, 2001
    Publication date: May 16, 2002
    Inventors: Woon-Yong Park, Hyeon-Hwan Kim, Dong-Hyeon Ki