Abstract: In the display apparatus, a gate driver receives at least one clock to sequentially provide gate lines in a display panel with a gate signal in a high state corresponding to a high interval of the clock. The gate driver includes a plurality of amorphous silicon transistors and is formed in the display panel through a thin film process. The clock has a delay time of about 2.0 ?s or less. If the delay time of the clock is reduced less than about 2.0 ?s, a threshold voltage margin of the transistors increases, so that the gate driver may not malfunction in a high temperature aging process. As a result, the gate driver may be prevented from malfunctioning in the high temperature aging process.

Abstract: A gate driver that comprises n shift registers, wherein n is an integer equal to or larger than 1, each of the n shift registers includes; a start stage which outputs a gate signal and starts its operation in response to a start signal, and a plurality of subsequent stages which are connected to each other in sequence, and which sequentially output a plurality of gate signals in response to a signal output from the start stage, wherein at least one stage of the plurality of subsequent stages is reset by the start signal.

Abstract: In the display apparatus, a gate driver receives at least one clock to sequentially provide gate lines in a display panel with a gate signal in a high state corresponding to a high interval of the clock. The gate driver includes a plurality of amorphous silicon transistors and is formed in the display panel through a thin film process. The clock has a delay time of about 2.0 ?s or less. If the delay time of the clock is reduced less than about 2.0 ?s, a threshold voltage margin of the transistors increases, so that the gate driver may not malfunction in a high temperature aging process. As a result, the gate driver may be prevented from malfunctioning in the high temperature aging process.

Abstract: A gate driver that comprises n shift registers, wherein n is an integer equal to or larger than 1, each of the n shift registers includes; a start stage which outputs a gate signal and starts its operation in response to a start signal, and a plurality of subsequent stages which are connected to each other in sequence, and which sequentially output a plurality of gate signals in response to a signal output from the start stage, wherein at least one stage of the plurality of subsequent stages is reset by the start signal.