Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

Abstract: A semiconductor memory device includes a memory chip defined with a first pad on one surface thereof; and a circuit chip defined with a second pad which is coupled with the first pad, on one surface thereof bonded with the one surface of the memory chip. The memory chip comprising: a memory cell array; a bit line disposed in a first wiring layer between the one surface and the memory cell array, and separated into a first bit line section and a second bit line section; and a power pad disposed in a space between the first bit line section and the second bit line section in the first wiring layer, and coupled with the first pad.

Abstract: The present disclosure relates to an apparatus and method for controlling steering of a platooning vehicle to prevent a trailer from departing from the road on a curved road by controlling steering of a tractor in consideration of a distance between the center of an overall width of the trailer and a left lane and a distance between the center of the overall width of the trailer and a right lane.

Abstract: A semiconductor memory device includes a memory structural body including first and second planes each of which includes memory cells coupled to word lines extending in a first direction and bit lines extending in a second direction and which are disposed along the first direction; and a logic structural body disposed between a substrate and the memory structural body, and including a row decoder. The row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit. The block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and the pass transistor circuit is disposed in an interval region between the first and second plane regions.

Abstract: A semiconductor memory device includes a plurality of bit lines electrically coupled to a memory cell array and extending in a first direction; bit line contact pads formed on a first plane over a substrate and respectively coupled to the bit lines through bit line contacts; and first contact pads formed on the first plane, respectively coupled to the bit line contact pads through redistribution lines, and electrically coupled to a page buffer circuit which is disposed on the substrate, through first contacts, wherein at least two first contact pads corresponding to at least two bit line contact pads which are disposed in a line in a second direction crossing with the first direction are disposed in a line in the first direction.

Abstract: A negative electrode active material including silicon-based active material particles each including a core including SiOx, wherein 0?x?2, and a coating layer present on the core. Also, a negative electrode active material in which the coating layer is any one of a carbon coating layer or a polymer coating layer, and the coating layer includes a fluorinated material including at least one of an alkali metal or an alkaline earth metal.

Abstract: A negative electrode active material as well as a method of preparing a negative electrode active material which includes preparing a silicon-based compound including SiOx, wherein 0.5<x<1.3; disposing a polymer layer including a polymer compound on the silicon-based compound; disposing a metal catalyst layer on the polymer layer; heat treating the silicon-based compound on which the polymer layer and the metal catalyst layer are disposed; and removing the metal catalyst layer, wherein the polymer compound includes any one selected from the group consisting of glucose, fructose, galactose, maltose, lactose, sucrose, a phenolic resin, a naphthalene resin, a polyvinyl alcohol resin, a urethane resin, polyimide, a furan resin, a cellulose resin, an epoxy resin, a polystyrene resin, a resorcinol-based resin, a phloroglucinol-based resin, a coal-derived pitch, a petroleum-derived pitch, a tar and a mixture of two or more thereof.

Abstract: A semiconductor memory device includes a logic structure including a peripheral circuit element which is formed over a substrate, a bottom dielectric layer which covers the peripheral circuit element and a bottom wiring line which is disposed in the bottom dielectric layer and is coupled to the peripheral circuit element; a memory structure stacked over the logic structure in a first direction perpendicular to a top surface of the substrate; a bit line disposed over a first top dielectric layer which covers the memory structure, extending in a second direction parallel to the top surface of the substrate, and divided into first and second bit line sections; and a power pad disposed over the first top dielectric layer between the first bit line section and the second bit line section, and coupled to the bottom wiring line through a power coupling contact which passes through the memory structure.

Abstract: An X-ray detector, an X-ray photographing apparatus including the X-ray detector, and a method of manufacturing the X-ray detector are provided. The X-ray detector includes a photoconversion layer configured to convert an X-ray into light having a wavelength range that is different from a wavelength range of the X-ray, a sensing layer arranged on the photoconversion layer and including a plurality of pixels configured to output the light as an electrical signal, a protective layer arranged on the sensing layer and protecting the sensing layer from physical shocks, and an anti-static layer arranged on the protective layer and preventing an electrostatic charge from being introduced into the sensing layer.

Abstract: A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction perpendicular to the first direction; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein the page buffer circuit is divided into a plurality of page buffer regions and is laid out at both sides of the cache circuit in the first direction.

Abstract: An LED lighting device is provided. The LED lighting device may include a light source configured to emit a light of first color temperature, second color temperature, and third color temperature and a switch electrically connected to the light source to control the light source to emit the lights of the first color temperature, the second color temperature, and the third color temperature, respectively. The light source includes a first light source configured to emit a light of a first color temperature, and a second light source configured to emit a light of a second color temperature that is different from the first color temperature, and the light source emits a light of a third color temperature between the first and second color temperatures when the switch parallel-connects the first light source and the second light source.

Abstract: A memory device includes a plurality of bit lines; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein a number of stages of the page buffer circuit is less than a number of stages of the cache circuit.

Abstract: A semiconductor memory device includes a memory structural body including first and second planes each of which includes memory cells coupled to word lines extending in a first direction and bit lines extending in a second direction and which are disposed along the first direction; and a logic structural body disposed between a substrate and the memory structural body, and including a row decoder. The row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit. The block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and the pass transistor circuit is disposed in an interval region between the first and second plane regions.

Abstract: A semiconductor memory device includes first and second memory blocks each including conductive and dielectric layers alternately stacked over a semiconductor layer disposed over a substrate, and disposed adjacent to each other in a first direction; a dummy block disposed over the semiconductor layer, and provided between the first and second memory blocks; first pass transistors formed over the substrate below the first memory block, and coupled to conductive layers, respectively, of the first memory block; second pass transistors formed over the substrate below the second memory block, and coupled to conductive layers, respectively, of the second memory block; bottom global row lines between the first and second pass transistors and the semiconductor layer, and each coupled to one of the first pass transistors and one of the second pass transistors; and top global row lines formed over the dummy block, and coupled to the bottom global row lines.

Abstract: The present invention relates to a negative electrode active material for a lithium secondary battery, which includes (A) first artificial graphite having an average particle diameter (D50) of 15 ?m to 20 ?m and (B) second artificial graphite having an average particle diameter (D50) of 3 ?m to 5 ?m, wherein the first artificial graphite (A) includes a secondary artificial graphite particle, in which at least one primary artificial graphite particle is agglomerated, and a carbon coating layer, and a weight ratio of the first artificial graphite to the second artificial graphite is in a range of 85:15 to 95:5, a negative electrode including the same, and a lithium secondary battery including the negative electrode.

Abstract: A negative electrode active material including a core having SiOx (0?x<2), an intermediate layer covering at least a portion of a surface of the core and including at least one of silicon nitride or silicon oxynitride, and a carbon coating layer covering at least a portion of the intermediate layer and containing nitrogen.

Abstract: A platooning control apparatus includes: a communication device configured to perform communication between a leading vehicle and following vehicles, which follow the leading vehicle, in a platoon; and a controller configured to control platooning by requesting checking of functions of the following vehicles through the communication device after the platoon is formed, by identifying whether a specific function among checked functions of the following vehicles operates, and by determining whether the platoon is maintained according to an identification result.

Abstract: A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.

Abstract: A semiconductor memory device comprises a memory cell array disposed on a substrate, a plurality of bit lines disposed on the a memory cell array, each bit line extending in a first direction parallel to the top surface of the substrate and divided into a first bit line section and a second bit line section, and a plurality of source line pads disposed at the same layer as the bit lines between the first bit line sections of the bit lines and the second bit line sections of the bit lines.

Abstract: Provided is a virtual experience device for aviation leisure sports, the device including: a main frame configured to form a vertical pillar and having an accommodation space in a region of an inside of the main frame; a bottom frame connected to the main frame and configured to form a bottom surface of the virtual experience device for aviation leisure sports; an upper frame extending from the main frame in a horizontal direction and having an accommodation space in a region of an inside of the upper frame and at least one through hole formed in a bottom surface of the upper fame; side frames installed at both sides of the upper frame and configured to support a load of the upper frame; and at least one roller provided in the accommodation space of the upper frame and configured to change a progression direction of a traction wire connected to Hanes that will be put on by a user for a leisure sports aircraft virtual experience, wherein a motor portion for adjusting a usage length of the traction wire is prov