Patents by Inventor Dong Hyun Baik

Dong Hyun Baik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11958874
    Abstract: According to the embodiment of the present disclosure, an organo tin compound is represented by the following Chemical Formula 1: In Chemical Formula 1, L1 and L2 are each independently selected from an alkoxy group having 1 to 10 carbon atoms and an alkylamino group having 1 to 10 carbon atoms, R1 is a substituted or unsubstituted aryl group having 6 to 8 carbon atoms, and R2 is selected from a substituted or unsubstituted linear alkyl group having 1 to 4 carbon atoms, a branched alkyl group having 3 to 4 carbon atoms, a cycloalkyl group having 3 to 6 carbon atoms, and an allyl group having 2 to 4 carbon atoms.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: April 16, 2024
    Assignees: EGTM Co., Ltd., SK hynix Inc.
    Inventors: Jang Keun Sim, Sung Jun Ji, Tae Young Lee, Shin Beom Kim, Sun Young Baik, Tae Hwan Lim, Dong Kyun Lee, Sang Hyun Lee, Su Pill Chun
  • Patent number: 7665001
    Abstract: A scan cell is described for testing an integrated circuit. The scan cell may include circuitry adapted to operate in a non-test mode as a storage element and adapted to operate as a static random access memory (SRAM) cell in a test mode. For example, the circuitry may include one or more pass transistors and a flip flop. The scan cell may be one of a plurality of addressable scan cells in one or more grids for testing the integrated circuit. For example, the scan cells may be arranged in a single grid or may be partitioned into two or more grids. The scan cell may be used for reliability testing or for performance testing. The PRAS cell for performance testing may be staged, with a first pattern applied and then a second pattern applied. For example, one section of the scan cell may operate using a clock cycle of ?1 and another section of the PRAS cell may operate using a clock cycle of ?2 which is different from ?1.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: February 16, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Dong Hyun Baik, Kewal K. Saluja
  • Publication number: 20080091995
    Abstract: A scan cell is described for testing an integrated circuit. The scan cell may include circuitry adapted to operate in a non-test mode as a storage element and adapted to operate as a static random access memory (SRAM) cell in a test mode. For example, the circuitry may include one or more pass transistors and a flip flop. The scan cell may be one of a plurality of addressable scan cells in one or more grids for testing the integrated circuit. For example, the scan cells may be arranged in a single grid or may be partitioned into two or more grids. The scan cell may be used for reliability testing or for performance testing. The PRAS cell for performance testing may be staged, with a first pattern applied and then a second pattern applied. For example, one section of the scan cell may operate using a clock cycle of ?1 and another section of the PRAS cell may operate using a clock cycle of ?2 which is different from ?1.
    Type: Application
    Filed: September 25, 2006
    Publication date: April 17, 2008
    Inventors: Dong Hyun Baik, Kewal K. Saluja