Abstract: An electronic apparatus, including an emissive display configured to provide a first image having a first image quality; a transparent display disposed on the emissive display and configured to provide a second image having a second image quality; and a controller configured to control the emissive display to provide the first image in according to first mode and control the transparent display to provide the second image according to a second mode.

Abstract: A home appliance is provided. The home appliance includes a main body having an opening, a door disposed on one side of the main body, the door being configured to open or close the opening, and a damping assembly configured to be operated by the door. The damping assembly includes a first lever installed in the main body, the first lever being configured to be movable when the door is pressed, a second lever connected to the first lever, and a cylinder connected to the second lever, the cylinder being configured to be movable in a direction that is parallel to a movement path of the first lever.

Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Abstract: An electronic apparatus, including an emissive display configured to provide a first image having a first image quality; a transparent display disposed on the emissive display and configured to provide a second image having a second image quality; and a controller configured to control the emissive display to provide the first image in according to first mode and control the transparent display to provide the second image according to a second mode.

Abstract: A range hood and a method for controlling the range hood are provided. The apparatus includes a range hood which is capable of photographing a cooking process that is being performed on an upper plate of a cook top by using a camera disposed in the main body of the range hood, and a method for controlling the range hood are provided. In some of the example embodiments, a range hood is capable of photographing a cooking process that is being performed on an upper plate of a cook top that is positioned below a bottom surface of the main body.

Abstract: The disclosed embodiments provide a smart garment on which implemented designs can be changed in terms of color, image, text, etc. Also, a system is provided that comprises: a server for providing various designs to be implemented on a smart garment; and a user terminal that can change the design of the smart garment by receiving various designs from the server and transmitting same to the smart garment. The system according to the disclosed embodiments comprises: a server including a design database for a smart garment; a user terminal for downloading a design for the smart garment from the server; and the smart garment on which the design transmitted from the user terminal is implemented.

Abstract: An aspect of the present disclosure is to provide a display apparatus capable of performing an information display function and a mirror function. Another aspect of the present disclosure is to provide a display apparatus of displaying a predetermined object in a turned-off state. Another aspect of the present disclosure is to provide a display apparatus including partition walls disposed in space between electrodes of a cholesteric Liquid Crystal Display (LCD) device. Another aspect of the present disclosure is to provide a transparent display apparatus with improved visibility using cholesteric liquid crystals. Disclosed is a display apparatus includes a reflective layer; and a liquid crystal layer disposed in front of the reflective layer, and configured to be converted between a transmissive mode for transmitting outside light, a display mode for reflecting outside light to display an object, and a transflective mode for transmitting outside light and reflecting outside light at a predetermined area.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: An electronic apparatus, including an emissive display configured to provide a first image having a first image quality; a transparent display disposed on the emissive display and configured to provide a second image having a second image quality; and a controller configured to control the emissive display to provide the first image in according to first mode and control the transparent display to provide the second image according to a second mode.

Abstract: A display module configured to improve transmission and reception performance of an electronic device includes: a first panel; a second panel disposed to be opposite to the first panel; and an antenna layer disposed between the first panel and the second panel, and comprising a resin layer formed by an imprinting method, wherein the resin layer includes: an engraved pattern formed in one surface; and an ink layer formed with a conductive material filled in the engraved pattern.

Abstract: A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Abstract: A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: A magneto-resistive random access memory (MRAM) including an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit including a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.

Abstract: A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.