Abstract: A timing controller for a display apparatus includes a dithering unit outputting a first signal in which bit widths of image signals are reduced, an image pattern detector detecting an image pattern of the image signals and outputting a dithering off signal corresponding to the detected image pattern, a dithering selector receiving the first signal and converts the first signal to a second signal in response to the dithering off signal, and a response time compensator generating a present image signal from the second signal and compensates a liquid crystal response time in accordance with a difference between the present image signal and a first previous image signal to output a data signal.

Abstract: A driving unit of display panel includes a data driving part, a timing controlling part and a gate driving part. The data driving part is configured to receive reference image data and includes a first data driving circuit part having a first channel outputting a first reference data signal based on the reference image data and a k-th channel outputting a k-th reference data signal based on the reference image data. The timing controlling part is configured to detect a time difference between the first reference data signal and the k-th reference data signal. The gate driving part is configured to output a gate signal to each of gate lines. By delaying data signals based on the gate signal delay caused by long line load and RC delay, the present invention may improve display quality of a display device.

Abstract: Disclosed is a display apparatus including: a display panel including pixels connected with a plurality of gate lines and a plurality of data lines; a gate driver supplying gate signals to the gate lines; and a data driver supplying data voltages to the data lines. The data driver includes a temperature measurer generating a temperature signal of the data driver.

Abstract: A display apparatus includes a first interpolator configured to generate first correction data for a first polarity corresponding to an input data using a first look up table which stores correction data for the first polarity compensating for a luminance difference between the first polarity and a second polarity opposite to the first polarity of a data voltage for the sub pixel, a first delay compensator configured to apply a correction value to the first correction data for the first polarity and generate second correction data for the first polarity, the correction value compensating for an RC delay based on a pixel position corresponding to the input data.

Abstract: A display device includes a display panel including gate lines, data lines, and pixels each connected to a corresponding gate line and a corresponding data line, a gate driver configured to drive the gate lines, a data driver configured to drive the data lines, and a timing controller configured to generate control signals to control the data driver and to apply a vertical synchronization start signal including a first pulse, a second pulse, a first gate pulse signal, and a second gate pulse signal to the gate driver. The gate driver applies gate driving signals to the gate lines to pre-charge the pixels in response to the first pulse of the vertical synchronization start signal and the first gate pulse signal, and to main-charge the pixels in response to the second pulse of the vertical synchronization start signal and the second gate pulse signal.

Abstract: An apparatus for monitoring pixel data includes a multiplexer configured to select pixel data applied to at least one of function blocks which is configured to convert the pixel data provided from an external device and adjust characteristics of a display device, a monitoring module configured to store the pixel data selected by the multiplexer, and an analyzing module configured to output a location selection signal to the multiplexer which provides the monitoring module with the pixel data based on the location selection signal, to read out the pixel data stored in the monitoring module by applying a pixel position signal to the monitoring module, and to analyze a variation of the read out pixel data.

Abstract: A display device includes a display panel and a signal controller. The signal controller receives an input signal and controls an operation of the display panel. The signal controller controls the display panel to display different images according to different types of a fail when determining the fail in the input signal.

Abstract: A semiconductor device includes a circuit board including a ground portion, and a semiconductor package disposed on the circuit board. The semiconductor package includes an external connecting pad and an exposed pad. The exposed pad and the ground portion are electrically connected at a first surface of the exposed pad. A semiconductor chip is disposed on a second surface of the exposed pad and electrically connected to the external connecting pad. The first surface of the exposed pad is located external to the semiconductor package, and the second surface of the exposed pad is located within the semiconductor package. A test pad is disposed on the semiconductor chip and is electrically connected to the exposed pad.

Abstract: A timing controller includes a receiver, an internal clock generator, a first frequency converter, a first selector and a control signal generator. The receiver receives an image signal and a main clock signal having a first spread spectrum frequency from an external system, converts the main clock signal to a converted main clock signal and the image signal to a first converted image signal, and outputs the converted main clock signal as a first clock signal having a plurality of frequencies. The internal clock generator multiplies the frequencies of the first clock signal and generates a second clock signal having a frequency band within the multiplied frequencies of the first clock signal. The first frequency converter converts the second clock signal to a third clock signal having a second spread spectrum frequency.

Abstract: A display apparatus includes a display panel, a plurality of gate lines driving circuit parts, a plurality of data lines driving circuit parts and a timing control part. The display panel includes a plurality of gate lines and a plurality of data lines. The gate lines driving circuit parts output gate signals to the gate lines. The data lines driving circuit parts output data signals to the data lines. The timing control part applies a dummy gate signal to at least one dummy gate line, controls a latch sequence of image data and an output sequence of the gate lines driving circuit parts in a reverse sequence, in response to an inverted-mounting mode selection signal for displaying an inverted mount image to the display panel. Because signal lines can be shortened, heat generated by the display apparatus may be decreased and image quality of the display apparatus may be improved.

Abstract: A display device includes a display panel including gate lines, data lines, and pixels each connected to a corresponding gate line and a corresponding data line, a gate driver configured to drive the gate lines, a data driver configured to drive the data lines, and a timing controller configured to generate control signals to control the data driver and to apply a vertical synchronization start signal including a first pulse, a second pulse, a first gate pulse signal, and a second gate pulse signal to the gate driver. The gate driver applies gate driving signals to the gate lines to pre-charge the pixels in response to the first pulse of the vertical synchronization start signal and the first gate pulse signal, and to main-charge the pixels in response to the second pulse of the vertical synchronization start signal and the second gate pulse signal.

Abstract: A timing controller for a display apparatus includes a dithering unit outputting a first signal in which bit widths of image signals are reduced, an image pattern detector detecting an image pattern of the image signals and outputting a dithering off signal corresponding to the detected image pattern, a dithering selector receiving the first signal and converts the first signal to a second signal in response to the dithering off signal, and a response time compensator generating a present image signal from the second signal and compensates a liquid crystal response time in accordance with a difference between the present image signal and a first previous image signal to output a data signal.

Abstract: A display apparatus includes a driving part and a display panel. The driving part includes a master timing controller and at least one slave timing controller synchronized with the master timing controller using a first data enable signal received by the master timing controller and a second data enable signal received by the slave timing controller. The display panel displays a first image on a first display block, and displays a second image on a second display block using the master timing controller.

Abstract: A method of restoring a timing controller includes generating an error condition signal from a timing controller by checking abnormality of an image signal and a control signal provided from an image board, feeding back the error condition signal to the image board, and restoring the timing controller based on the error condition signal.

Abstract: The present invention relates to a display apparatus to synchronize a synchronous signal and an inverter driving signal in response to a display mode, and a control method thereof. A back light unit of the display apparatus makes a back light to dim based on an inverter driving signal, and a dimming frequency of the back light varies in response to a synchronous signal frequency of the image. When a synchronous signal having an abnormal frequency is inputted to the back light unit for several seconds, the back light unit holds the frequency of the inverter driving signal and the frequency of the inverter driving signal varies smoothly in response to the display mode.

Abstract: A semiconductor device includes a circuit board including a ground portion, and a semiconductor package disposed on the circuit board. The semiconductor package includes an external connecting pad and an exposed pad. The exposed pad and the ground portion are electrically connected at a first surface of the exposed pad. A semiconductor chip is disposed on a second surface of the exposed pad and electrically connected to the external connecting pad. The first surface of the exposed pad is located external to the semiconductor package, and the second surface of the exposed pad is located within the semiconductor package. A test pad is disposed on the semiconductor chip and is electrically connected to the exposed pad.

Abstract: A display apparatus includes; a display panel which displays an image in response to a gate voltage and a data voltage, a panel driver which receives a control signal, and which supplies the gate voltage and the data voltage to the display panel according to the control signal, a backlight which supplies a light to the display panel, an inverter which receives a backlight dimming signal, and which controls a brightness of a light emitted from the backlight according to the backlight dimming signal, and a timing controller which receives a synchronization signal, determines a frame frequency of the display panel according to the synchronization signal, outputs the control signal, and modulates the synchronization signal based on a ratio of a predetermined backlight dimming frequency to the frame frequency, and which outputs the backlight dimming signal according to the modulated synchronization signal.

Abstract: A timing controller includes a receiver, an internal clock generator, a first frequency converter, a first selector and a control signal generator. The receiver receives an image signal and a main clock signal having a first spread spectrum frequency from an external system, converts the main clock signal to a converted main clock signal and the image signal to a first converted image signal, and outputs the converted main clock signal as a first clock signal having a plurality of frequencies. The internal clock generator multiplies the frequencies of the first clock signal and generates a second clock signal having a frequency band within the multiplied frequencies of the first clock signal. The first frequency converter converts the second clock signal to a third clock signal having a second spread spectrum frequency.

Abstract: A method of restoring a timing controller includes generating an error condition signal from a timing controller by checking abnormality of an image signal and a control signal provided from an image board, feeding back the error condition signal to the image board, and restoring the timing controller based on the error condition signal.

Abstract: A display device includes a driving signal generator being supplied with a synchronous signal and a clock signal and generating an inverter driving signal having a given frequency that is multiplied by a predetermined ratio from a frequency of the synchronous signal, an inverter outputting a driving signal based on the inverter driving signal, and a backlight unit controlling turned-on or turned-off based on the driving signal from the inverter. The driving signal generator operates the number of clocks of the clock signal included in a predetermined period of the synchronous signal by using a predetermined value, defines a magnitude of each section of the inverter driving signal with respect to the predetermined period of the synchronous signal, and adjusts the section magnitude of the inverter driving signal when the number of clocks differs from the total section magnitude of the inverter driving signal based on the magnitude of each section.