Patents by Inventor Dong-Ick Lee
Dong-Ick Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220399229Abstract: A semiconductor device includes a substrate, a first interlayer insulating layer on the substrate, a lower wiring pattern inside the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer, a second interlayer insulating layer on the etch stop layer, a via trench inside the second interlayer insulating layer and the etch stop layer and that extends to the lower wiring pattern, a via inside the via trench and that is in contact with the second interlayer insulating layer and is formed of a single film, an upper wiring trench formed inside the second interlayer insulating layer on the via, and an upper wiring pattern inside the upper wiring trench and that includes an upper wiring barrier layer and an upper wiring filling layer on the upper wiring barrier layer An upper surface of the via is in contact with the upper wiring filling layer.Type: ApplicationFiled: February 4, 2022Publication date: December 15, 2022Inventors: SANG CHEOL NA, KI CHUL PARK, SEO WOO NAM, DONG ICK LEE
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Patent number: 10733354Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.Type: GrantFiled: December 19, 2018Date of Patent: August 4, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hojin Kim, Dongyue Yang, Dong-Ick Lee, Yue Zhou, Jae Ho Joung, Gregory Costrini, El Mehdi Bazizi, Dongsuk Park
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Publication number: 20200201955Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Hojin Kim, Dongyue Yang, Dong-Ick Lee, Yue Zhou, Jae Ho Joung, Gregory Costrini, El Mehdi Bazizi, Dongsuk Park
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Patent number: 10283617Abstract: Device structures and fabrication methods for a field-effect transistor. A first dielectric spacer adjacent to a sidewall of a gate placeholder structure. A contact placeholder structure is formed adjacent to the first dielectric spacer such that the first dielectric spacer is arranged laterally between the gate placeholder structure and the contact placeholder structure. The contact placeholder structure and the first dielectric spacer are recessed to open a space over the contact placeholder structure and the first dielectric spacer. A second dielectric spacer is formed in the space adjacent to the sidewall of the gate placeholder structure and over the first dielectric spacer.Type: GrantFiled: November 1, 2017Date of Patent: May 7, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Dong-Ick Lee, Min Gyu Sung, Chanro Park
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Publication number: 20190131430Abstract: Device structures and fabrication methods for a field-effect transistor. A first dielectric spacer adjacent to a sidewall of a gate placeholder structure. A contact placeholder structure is formed adjacent to the first dielectric spacer such that the first dielectric spacer is arranged laterally between the gate placeholder structure and the contact placeholder structure. The contact placeholder structure and the first dielectric spacer are recessed to open a space over the contact placeholder structure and the first dielectric spacer. A second dielectric spacer is formed in the space adjacent to the sidewall of the gate placeholder structure and over the first dielectric spacer.Type: ApplicationFiled: November 1, 2017Publication date: May 2, 2019Inventors: Ruilong Xie, Dong-Ick Lee, Min Gyu Sung, Chanro Park
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Patent number: 9818836Abstract: A method of manufacturing a FinFET structure involves forming a gate cut within a sacrificial gate layer and backfilling the gate cut opening with etch selective dielectric materials. Partial etching of one of the dielectric materials can be used to increase the distance between the gate cut (isolation) structure and an adjacent fin relative to methods that do not perform a backfilling step using etch selective materials.Type: GrantFiled: April 13, 2017Date of Patent: November 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Min Gyu Sung, Ruilong Xie, Chanro Park, Dong-Ick Lee
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Patent number: 9373696Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.Type: GrantFiled: February 9, 2015Date of Patent: June 21, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Christian Lavoie, Dong-Ick Lee, Ahmet S. Ozcan, Zhen Zhang
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Publication number: 20150155366Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.Type: ApplicationFiled: February 9, 2015Publication date: June 4, 2015Inventors: Christian Lavoie, Dong-Ick Lee, Ahmet S. Ozcan, Zhen Zhang
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Patent number: 8981565Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.Type: GrantFiled: March 23, 2012Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Christian Lavoie, Dong-Ick Lee, Ahmet Serkan Ozcan, Zhen Zhang
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Patent number: 8643122Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.Type: GrantFiled: December 6, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Emre Alptekin, Dong-Ick Lee, Viraj Y. Sardesai, Cung D. Tran, Jian Yu, Reinaldo A. Vega, Rajasekhar Venigalla
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Publication number: 20130249099Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.Type: ApplicationFiled: March 23, 2012Publication date: September 26, 2013Applicant: International Business Machines CorporationInventors: Christian Lavoie, Dong-Ick Lee, Ahmet Serkan Ozcan, Zhen Zhang
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Patent number: 8415250Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.Type: GrantFiled: April 29, 2011Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Emre Alptekin, Dong-Ick Lee, Viraj Yashawant Sardesai, Cung Do Tran, Jian Yu, Reinaldo Ariel Vega, Rajasekhar Venigalla
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Publication number: 20120273798Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emre Alptekin, Dong-Ick Lee, Viraj Yashawant Sardesai, Cung Do Tran, Jian Yu, Reinaldo Ariel Vega, Rajasekhar Venigalla
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Patent number: 8241981Abstract: A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.Type: GrantFiled: January 31, 2011Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Rishikesh Krishnan, Joseph F. Shepard, Jr., Michael P. Chudzik, Christian Lavoie, Dong-Ick Lee, Oh-Jung Kwon, Unoh Kwon, Youngjin Choi
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Publication number: 20120196424Abstract: A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rishikesh Krishnan, Joseph F. Shepard, JR., Michael P. Chudzik, Christian Lavoie, Dong-Ick Lee, Oh-Jung Kwon, Unoh Kwon, Youngjin Choi