Patents by Inventor Dong Ik SUH

Dong Ik SUH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240244826
    Abstract: A semiconductor device includes a substrate, a bit line conductive layer extending in a lateral direction substantially parallel to a surface of the substrate, a first insulation line structure extending in a second direction that is perpendicular to the first lateral direction and that is substantially parallel to the surface of the substrate, first and second channel structures that are disposed to respectively contact first and second sides of the first insulation line structure and that partially overlap with the bit line conductive layer, first and second gate dielectric layers respectively disposed over the substrate and on side surfaces of the first and second channel structures, and first and second gate line conductive layers extending in the second lateral direction over the substrate and covering at least a portion of each of the first and second gate dielectric layers, respectively.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Jae Hyun HAN, Dong Ik SUH, Jae Gil LEE
  • Patent number: 11974426
    Abstract: A semiconductor device includes a substrate, a bit line conductive layer disposed on the substrate and extending in a first lateral direction substantially parallel to a surface of the substrate, first and second channel structures disposed on the bit line conductive layer to be spaced apart from each other in the first lateral direction, first and second gate dielectric layers disposed on side surfaces of the first and second channel structures over the substrate, first and second gate line conductive layers disposed on the first and second gate dielectric layers, respectively, the first and second gate line conductive layers common to the first and second channel structures, respectively, and extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate, and first and second storage node electrode layers disposed over the first and second channel structures, respectively.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: April 30, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Hyun Han, Dong Ik Suh, Jae Gil Lee
  • Publication number: 20240081082
    Abstract: A semiconductor device according to an embodiment includes a first electrode and a second electrode that are spaced apart from each other, a capacitor dielectric structure disposed between the first electrode and the second electrode, and a barrier dielectric layer disposed between one of the first and second electrodes and the capacitor dielectric structure. The capacitor dielectric structure may include a ferroelectric layer and a dielectric layer. The barrier dielectric layer may include a ferroelectric material.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 7, 2024
    Inventors: Dong Ik SUH, Won Tae KOO
  • Publication number: 20240023343
    Abstract: A semiconductor device according to an embodiment includes a first electrode and a second electrode that are spaced apart from each other, and a dielectric structure disposed between the first electrode and the second electrode. The dielectric structure includes a barrier dielectric layer and a capacitor dielectric layer that are connected in series to each other. The barrier dielectric layer includes a ferroelectric material, and the capacitor dielectric layer includes a non-ferroelectric material.
    Type: Application
    Filed: November 29, 2022
    Publication date: January 18, 2024
    Applicant: SK hynix Inc.
    Inventors: Won Tae KOO, Dong Ik SUH
  • Patent number: 11792995
    Abstract: A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure respectively extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a first ferroelectric layer disposed on a first surface of the semiconductor layer, and a first gate electrode layer disposed on the first ferroelectric layer.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: October 17, 2023
    Assignee: SK hynix Inc.
    Inventors: Jae Gil Lee, Dong Ik Suh, Se Ho Lee
  • Publication number: 20230170381
    Abstract: A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode, a dielectric layer disposed on the ferroelectric layer, charge trap sites disposed in an inner region of the dielectric layer, and a second electrode disposed on the dielectric layer. The dielectric layer may have a non-ferroelectric property. The dielectric layer and the ferroelectric layer are disposed between the first electrode and the second electrode and connected in series to each other. The semiconductor device may include charge trap sites distributed in an inner region of the dielectric layer having a non-ferroelectric property.
    Type: Application
    Filed: May 6, 2022
    Publication date: June 1, 2023
    Inventors: Won Tae KOO, Dong Ik SUH
  • Patent number: 11664413
    Abstract: A semiconductor device may include: a first electrode; a second electrode; and a multilayer stack that is interposed between the first electrode and the second electrode and includes a seed layer and a high-k dielectric layer, wherein each of the seed layer and the high-k dielectric layer may have a rocksalt crystal structure, and wherein the high-k dielectric layer may exhibit a dielectric constant (k) of fifty (50) or higher.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: May 30, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Ik Suh, Se Ho Lee
  • Publication number: 20230103835
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes a substrate, a first epitaxial electrode layer disposed on the substrate, a ferroelectric epitaxial layer disposed on the first epitaxial electrode layer, a dielectric epitaxial layer disposed on the ferroelectric epitaxial layer, and a second epitaxial electrode layer disposed on the dielectric epitaxial layer. The ferroelectric epitaxial layer implements a negative capacitance. Each of the first and second epitaxial electrode layers includes conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are electrically connected in series is non-ferroelectric. A dielectric structure comprising the ferroelectric epitaxial layer and the dielectric epitaxial layer is non-ferroelectric.
    Type: Application
    Filed: March 11, 2022
    Publication date: April 6, 2023
    Inventors: Won Tae KOO, Dong Ik SUH
  • Publication number: 20230098622
    Abstract: A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode and implementing a negative capacitance, a dielectric structure disposed on the ferroelectric layer and including a first dielectric layer and a second dielectric layer that are alternately stacked, and a second electrode disposed on the dielectric structure. The ferroelectric layer and the dielectric structure are configured to be electrically connected in series to each other. The ferroelectric layer and dielectric structure together have a non-ferroelectric property.
    Type: Application
    Filed: May 19, 2022
    Publication date: March 30, 2023
    Inventors: Won Tae KOO, Dong Ik SUH, Se Ho LEE
  • Publication number: 20220189972
    Abstract: A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure respectively extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a first ferroelectric layer disposed on a first surface of the semiconductor layer, and a first gate electrode layer disposed on the first ferroelectric layer.
    Type: Application
    Filed: May 11, 2021
    Publication date: June 16, 2022
    Inventors: Jae Gil LEE, Dong Ik SUH, Se Ho LEE
  • Publication number: 20220122980
    Abstract: A semiconductor device includes a substrate, a bit line conductive layer disposed on the substrate and extending in a first lateral direction substantially parallel to a surface of the substrate, first and second channel structures disposed on the bit line conductive layer to be spaced apart from each other in the first lateral direction, first and second gate dielectric layers disposed on side surfaces of the first and second channel structures over the substrate, first and second gate line conductive layers disposed on the first and second gate dielectric layers, respectively, the first and second gate line conductive layers common to the first and second channel structures, respectively, and extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate, and first and second storage node electrode layers disposed over the first and second channel structures, respectively.
    Type: Application
    Filed: March 12, 2021
    Publication date: April 21, 2022
    Inventors: Jae Hyun HAN, Dong Ik SUH, Jae Gil LEE
  • Publication number: 20210408222
    Abstract: A semiconductor device may include: a first electrode; a second electrode; and a multilayer stack that is interposed between the first electrode and the second electrode and includes a seed layer and a high-k dielectric layer, wherein each of the seed layer and the high-k dielectric layer may have a rocksalt crystal structure, and wherein the high-k dielectric layer may exhibit a dielectric constant (k) of fifty (50) or higher.
    Type: Application
    Filed: January 6, 2021
    Publication date: December 30, 2021
    Inventors: Dong Ik SUH, Se Ho LEE