Abstract: A semiconductor memory device having normal columns and redundant columns includes normal column decoders for designating the normal columns and redundant column decoders for designating the redundant columns so that the bits from the normal columns are combined with the bits from the redundant columns so as to provide an entire byte. The normal column decoders are to be operated simultaneously with the redundant column decoders.

Abstract: Disclosed is a layout method for increasing pitches between bit lines and between sense amplifiers so as to easily accomplish fabrication of a semiconductor memory device and a semiconductor memory array capable of reducing the number of sense amplifiers. The semiconductor memory array includes a plurality of bit lines, and a plurality of sense amplifiers, each sense amplifier being connected to each pair of the bit lines, wherein the sense amplifiers placed in each column make up each group, with odd pairs of the bit lines being connected to even or odd sense amplifier groups, and even pairs of the bit lines being connected to even or odd sense amplifier groups.

Abstract: A higher packing of cells in a memory circuit includes a plurality of word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.