Abstract: An image sensor and an operating method thereof are provided. The image sensor comprises a voltage generator configured to receive a reference voltage and generate an operating voltage, an analog-to-digital converter (ADC) circuit configured to receive the operating voltage and output a digital code based on the operating voltage, and processing circuitry configured to receive the digital code, and calculate a settling time at which the operating voltage was stabilized based on the digital code and a desired settling threshold voltage value.

Abstract: An image sensor is provided. The image sensor includes a pixel array including first and second pixels, the first and second pixels receiving the same transfer gate signal and outputting first and second signal voltages, respectively, a transfer gate driver receiving first and second voltages and generating the transfer gate signal, the transfer gate signal having the first voltage as its maximum voltage and having the second voltage as its minimum voltage and a compensation module detecting a variation in the second voltage, generating a compensation voltage based on the variation in the second voltage, and performing a compensation operation.

Abstract: An image sensor is provided. The image sensor includes a pixel array including first and second pixels, the first and second pixels receiving the same transfer gate signal and outputting first and second signal voltages, respectively, a transfer gate driver receiving first and second voltages and generating the transfer gate signal, the transfer gate signal having the first voltage as its maximum voltage and having the second voltage as its minimum voltage and a compensation module detecting a variation in the second voltage, generating a compensation voltage based on the variation in the second voltage, and performing a compensation operation.

Abstract: An image sensor is provided. The image sensor includes a pixel array including first and second pixels, the first and second pixels receiving the same transfer gate signal and outputting first and second signal voltages, respectively, a transfer gate driver receiving first and second voltages and generating the transfer gate signal, the transfer gate signal having the first voltage as its maximum voltage and having the second voltage as its minimum voltage and a compensation module detecting a variation in the second voltage, generating a compensation voltage based on the variation in the second voltage, and performing a compensation operation.

Abstract: A charge pump provides an output voltage with reduced voltage ripple. The charge pump includes a first capacitor, a second capacitor, and a control circuit. The control circuit charges the first capacitor to one of a first voltage and a second voltage and the second capacitor to the other one of the first and second voltages using differential clock signals and an input voltage during each clock phase and outputs the higher one of the first and second voltages as an output voltage.

Abstract: An image sensor is provided. The image sensor includes a pixel array including first and second pixels, the first and second pixels receiving the same transfer gate signal and outputting first and second signal voltages, respectively, a transfer gate driver receiving first and second voltages and generating the transfer gate signal, the transfer gate signal having the first voltage as its maximum voltage and having the second voltage as its minimum voltage and a compensation module detecting a variation in the second voltage, generating a compensation voltage based on the variation in the second voltage, and performing a compensation operation.

Abstract: A charge pump provides an output voltage with reduced voltage ripple. The charge pump includes a first capacitor, a second capacitor, and a control circuit. The control circuit charges the first capacitor to one of a first voltage and a second voltage and the second capacitor to the other one of the first and second voltages using differential clock signals and an input voltage during each clock phase and outputs the higher one of the first and second voltages as an output voltage.