Abstract: A semiconductor memory device, and a method of operating the same, includes a memory block including a plurality of pages, a read and write circuit configured to apply a first bit line voltage to a selected bit line corresponding to a selected memory cell and apply a second bit line voltage having a potential lower than that of the first bit line voltage to an unselected bit line during detrap operation, a voltage generation circuit configured to generate a first set voltage, a second set voltage, and a pass voltage during the detrap operation, and an address decoder configured to apply the first set voltage to a selected word line corresponding to the selected page and apply the second set voltage having a potential higher than that of the first set voltage to unselected word lines, during the detrap operation.

Abstract: The present technology includes a memory device, a memory system including the memory device, and a test operation of the memory device. The memory device includes a memory block connected to word lines and select lines, a bit line connected to the memory block, a voltage generator configured to generate a test voltage to be applied to a selected line among the word lines and the select lines, a page buffer configured to sense a voltage of the bit line to store and output test data, and a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data.

Abstract: The present technology includes a memory device, a memory system including the memory device, and a test operation of the memory device. The memory device includes a memory block connected to word lines and select lines, a bit line connected to the memory block, a voltage generator configured to generate a test voltage to be applied to a selected line among the word lines and the select lines, a page buffer configured to sense a voltage of the bit line to store and output test data, and a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data.

Abstract: Provided herein is a memory device that may include a plurality of memory cells coupled to a plurality of bit lines and a common source line. The memory device may also include a control circuit configured to control a peripheral circuit to perform a program operation that includes two or more program steps on selected memory cells of a selected word line. The peripheral circuit may be configured to perform a first program step of the two or more program steps on the selected memory cells, then perform a detrap operation that applies a detrap voltage to the plurality of bit lines and the common source line for a predefined time, and thereafter perform a second program step of the two or more program steps on the selected memory cells.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory device may include memory cells respectively connected to a plurality of word lines, a peripheral circuit configured to perform a read operation of reading data stored in selected memory cells connected to a selected word line among the memory cells, and a read operation controller configured to control the peripheral circuit to apply a pass voltage to adjacent word lines adjacent to the selected word line during the read operation, discharge the pass voltage to a target pass voltage less than the pass voltage after a predetermined time elapses, and obtain data stored in the selected memory cells through bit lines connected to the selected memory cells after a target read time elapses, after a voltage applied to the adjacent word lines is discharged to the target pass voltage.

Abstract: A semiconductor memory device, and a method of operating the same, includes a memory block including a plurality of pages, a read and write circuit configured to apply a first bit line voltage to a selected bit line corresponding to a selected memory cell and apply a second bit line voltage having a potential lower than that of the first bit line voltage to an unselected bit line during detrap operation, a voltage generation circuit configured to generate a first set voltage, a second set voltage, and a pass voltage during the detrap operation, and an address decoder configured to apply the first set voltage to a selected word line corresponding to the selected page and apply the second set voltage having a potential higher than that of the first set voltage to unselected word lines, during the detrap operation.

Abstract: Provided herein is a memory device that may include a plurality of memory cells coupled to a plurality of bit lines and a common source line. The memory device may also include a control circuit configured to control a peripheral circuit to perform a program operation that includes two or more program steps on selected memory cells of a selected word line. The peripheral circuit may be configured to perform a first program step of the two or more program steps on the selected memory cells, then perform a detrap operation that applies a detrap voltage to the plurality of bit lines and the common source line for a predefined time, and thereafter perform a second program step of the two or more program steps on the selected memory cells.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory device may include memory cells respectively connected to a plurality of word lines, a peripheral circuit configured to perform a read operation of reading data stored in selected memory cells connected to a selected word line among the memory cells, and a read operation controller configured to control the peripheral circuit to apply a pass voltage to adjacent word lines adjacent to the selected word line during the read operation, discharge the pass voltage to a target pass voltage less than the pass voltage after a predetermined time elapses, and obtain data stored in the selected memory cells through bit lines connected to the selected memory cells after a target read time elapses, after a voltage applied to the adjacent word lines is discharged to the target pass voltage.

Abstract: The present technology includes a memory device, a memory system including the memory device, and a test operation of the memory device. The memory device includes a memory block connected to word lines and select lines, a bit line connected to the memory block, a voltage generator configured to generate a test voltage to be applied to a selected line among the word lines and the select lines, a page buffer configured to sense a voltage of the bit line to store and output test data, and a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including super blocks, each of the super blocks including a plurality of memory blocks, and a controller configured to control the memory device so that a program operation is performed on a selected memory block within any one of the super blocks based on a request from a host, wherein, when a program fail occurs during the program operation that is performed on the selected memory block of the selected super block, the controller is configured to control the memory device so that a test read operation is performed on remaining memory blocks, besides the selected memory block, of the selected super block.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including super blocks, each of the super blocks including a plurality of memory blocks, and a controller configured to control the memory device so that a program operation is performed on a selected memory block within any one of the super blocks based on a request from a host, wherein, when a program fail occurs during the program operation that is performed on the selected memory block of the selected super block, the controller is configured to control the memory device so that a test read operation is performed on remaining memory blocks, besides the selected memory block, of the selected super block.

Abstract: The semiconductor memory device may include a memory cell array and a peripheral circuit. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a multi-page read operation on a selected memory block among the plurality of memory blocks. The peripheral circuit may select a first word line and a second word line, which are coupled to the selected memory block, and perform the multi-page read operation on the first and second word lines.

Abstract: The semiconductor memory device may include a memory cell array and a peripheral circuit. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a multi-page read operation on a selected memory block among the plurality of memory blocks. The peripheral circuit may select a first word line and a second word line, which are coupled to the selected memory block, and perform the multi-page read operation on the first and second word lines.