Abstract: A display apparatus and a method for displaying a menu are provided. The display apparatus displays a content image on a first area of the entire screen area at a specific screen ratio and displays a menu comprising a plurality of pages on a second area corresponding to an area excluding the first area where the content image is displayed. Accordingly, the display apparatus may display a menu without blocking the content image or deteriorating quality of the content image.

Abstract: The power supply includes: an electromagnetic interference filter including a first filter which has a pair of electromagnetically coupled cores having at least two leg parts, first and second bobbins each having a tube-shaped body part having a penetration hole into which each of the leg parts is inserted and having a winding region defined as the circumference of the outer peripheral surface of the body part, and first and second coils respectively wound around the first and second bobbins to remove common mode electromagnetic interference included in power transmitted from a power line, the electromagnetic interference filter removing differential mode electromagnetic interference due to leakage inductance formed due to the leakage of magnetic flux flowing through the cores; a power factor corrector correcting a power factor of the power where the electromagnetic interference is removed; and a power converter switching the power-factor-corrected power into a driving power having a predetermined voltage lev

Abstract: A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer.

Abstract: A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

Abstract: Disclosed herein is a photonic crystal waveguide inlet structure for improving coupling efficiency of a strip waveguide and a photonic crystal waveguide. The photonic crystal waveguide inlet structure includes an inlet region of the photonic crystal waveguide. The photonic crystal waveguide includes photonic crystals in which air holes are arranged in a triangle lattice shape in a dielectric, and a hybrid waveguide in which at least one of the air holes is removed, the hybrid waveguide spacing the inlet region apart from the strip waveguide.

Abstract: The present invention relates to esomeprazole free base or its alkali salt-containing composition which stability is improved and is easy to manufacture.

Abstract: Disclosed herein are an apparatus and method for detecting the survival status of a living thing. The apparatus for detecting the survival status of a living thing includes a tilt sensor, a determination unit, and a communication unit. The tilt sensor is attached to a target living thing, and detects minute vibrations generated by the motion of the target living thing. The determination unit determines the survival status of the target living thing for a preset update period based on the minute vibrations. The communication unit sends an update packet including determination results of the determination unit to an outside.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: Disclosed is a display apparatus including a first case and a second case coupled to each other to define an external appearance of the display apparatus. A fastening guide extends from an inner surface of the first case, and a fastening member is engaged with the fastening guide. The fastening member is provided with a boss portion for screw-fastening. The first case and second case are coupled to each other using the fastening guide and fastening member having a thin thickness, whereby a reduced thickness of fastening parts and stable inter-coupling of the first case and second case are accomplished.

Abstract: An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level.

Abstract: An image display device includes front and rear covers which surround a display panel and a plurality of connection members connected to the display panel and connected to each of the covers. Thereby, the display panel has a bezel part having a narrow width, and the front and rear covers are easily fixed to each other.

Abstract: A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

Abstract: An LCD device and a method of driving the same are disclosed, to improve a picture quality by realizing a rapid response speed, wherein the LCD device comprises an image display part which includes liquid crystal cells formed in respective regions defined by a plurality of gate and data lines; a timing controller which modulates data inputted according to a first frame frequency to modulation data to realize a rapid response speed of liquid crystal, and outputs the modulation data or data to a second frame frequency; a gate driver which generates gate on voltages under control of the timing controller, and supplies the gate on voltages to the gate lines in sequence; and a data driver which converts the modulation data or data supplied from the timing controller to a data voltage, and supplies the data voltage to the data line in synchronization with the gate on voltage.

Abstract: An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may be configured to generate signals for controlling ODT based on a second clock signal delay-locked to the external clock signal and the synchronous ODT command. The synchronous ODT command may be generated in a disabled period of the second clock signal.

Abstract: An optical disc drive, and a method of driving the optical disc drive are provided. Where the optical disc drive has a connectivity or a compatibility with a host that is incompatible with the optical disc drive, a file system and device information accepted by the host are provided. The host may have a compatibility with limited external medium devices and a specific command set for data exchange. The optical disc drive and the method of driving the optical disc drive may transmit compatible information to the host and select the specific command set accepted by the host, so that the optical disc drive is compatible with the host.

Abstract: A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

Abstract: A data storage system comprising a storage device comprising at least one nonvolatile memory, and a controller connected to the storage device through a channel. The memory controller sends part or all of a command, address and data for a next operation to the nonvolatile memory while the nonvolatile memory device is in a busy state. The memory controller then performs a background operation while the nonvolatile memory device remains in the busy state.

Abstract: Disclosed herein is a photonic crystal waveguide inlet structure for improving coupling efficiency of a strip waveguide and a photonic crystal waveguide. The photonic crystal waveguide inlet structure includes an inlet region of the photonic crystal waveguide. The photonic crystal waveguide includes photonic crystals in which air holes are arranged in a triangle lattice shape in a dielectric, and a hybrid waveguide in which at least one of the air holes is removed, the hybrid waveguide spacing the inlet region apart from the strip waveguide.