Patents by Inventor Dong Jin SEONG

Dong Jin SEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PCIe DEVICE AND COMPUTING SYSTEM INCLUDING THE SAME
    Publication number: 20250252023
    Abstract: A Peripheral Component Interconnect express (PCIe) device includes: a plurality of ports forming a plurality of lanes; and a link controller configured to set a link including the plurality of lanes to allocate non-sequential lane numbers to lanes adjacent to each other among the plurality of lanes.
    Type: Application
    Filed: March 26, 2025
    Publication date: August 7, 2025
    Inventors: Yong Tae JEON, Dong Jin SEONG, Jong Heon JEONG
  • PCIe device and computing system including the same
    Patent number: 12282398
    Abstract: A Peripheral Component Interconnect express (PCIe) device includes: a plurality of ports forming a plurality of lanes; and a link controller configured to set a link including the plurality of lanes to allocate non-sequential lane numbers to lanes adjacent to each other among the plurality of lanes.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: April 22, 2025
    Assignee: SK hynix Inc.
    Inventors: Yong Tae Jeon, Dong Jin Seong, Jong Heon Jeong
  • PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME
    Publication number: 20250103431
    Abstract: Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Inventors: Yong Tae JEON, Gil Bong PARK, Dong Jin SEONG
  • PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME
    Publication number: 20230385150
    Abstract: Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Yong Tae JEON, Gil Bong PARK, Dong Jin SEONG
  • PCIe DEVICE AND COMPUTING SYSTEM INCLUDING THE SAME
    Publication number: 20230315591
    Abstract: A Peripheral Component Interconnect express (PCIe) device includes: a plurality of ports forming a plurality of lanes; and a link controller configured to set a link including the plurality of lanes to allocate non-sequential lane numbers to lanes adjacent to each other among the plurality of lanes.
    Type: Application
    Filed: September 27, 2022
    Publication date: October 5, 2023
    Inventors: Yong Tae JEON, Dong Jin SEONG, Jong Heon JEONG
  • Peripheral component interconnect express interface device and system including the same
    Patent number: 11726870
    Abstract: Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: August 15, 2023
    Assignee: SK hynix Inc.
    Inventors: Yong Tae Jeon, Gil Bong Park, Dong Jin Seong
  • PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME
    Publication number: 20220261311
    Abstract: Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.
    Type: Application
    Filed: July 20, 2021
    Publication date: August 18, 2022
    Inventors: Yong Tae JEON, Gil Bong PARK, Dong Jin SEONG