Abstract: A semiconductor integrated circuit device may include a first protecting unit and a second protecting unit. The first protecting unit may include first to nth backward diodes serially connected between a pad and a first power line. The second protecting unit may include at least one forward diode connected between the pad and a second power line. The first backward diode and the forward diode connected to the pad may be integrated in one conductive well without a severance to face each other.

Abstract: A semiconductor integrated circuit device may include a first region, a second region, a pad structure and an electrostatic discharge (ESD) connection. The first region may be positioned adjacent to a semiconductor substrate. An ESD protection circuit may be integrated in the first region. The second region may be stacked on the first region. A plurality of memory cells may be formed in the second region. The pad structure may be arranged over the second region to receive an external voltage. The ESD connection may include a plurality of lower conductive wirings in the first region. At least one of the lower conductive wirings may be electrically connected with the ESD protection circuit. The at least one of the lower conductive wirings may be drawn to a portion corresponding to the pad structure.

Abstract: An electrostatic discharge protection device includes first and second wells of a first conductivity type, the first and second wells having different impurity doping concentrations, respectively, a gate formed on the first well, a source region of a second conductivity type formed at one side of the gate in the first well, a drift region of the second conductivity type formed at the other side of gate and over both of the first well and the second well, and a drain region of the second conductivity type formed in the drift region of the second well.

Abstract: An integrated circuit includes an input/output pad for signal exchange with an external circuit, an electrostatic discharge (ESD) protection unit coupled to the input/output pad and configured to form an ESD path between a first voltage line and a second voltage line, a first drive transistor coupled between the first voltage line and the input/output pad, a first driving control unit coupled to a gate of the first drive transistor and configured to control the first drive transistor, a first dummy drive transistor coupled between the first voltage line and the input/output pad, and a first auxiliary driving control unit configured to supply the first voltage to a gate of the first dummy drive transistor in a normal operation mode, and float the gate of the first dummy drive transistor in a non-operation mode in which no power is supplied.

Abstract: An electrostatic discharge protection device includes a first well comprising a MOS transistor; a second well comprising a first impurity region to which a first voltage is applied, and a second impurity region connected to an input/output pad, the second well being disposed adjacent to the first well; and a third well comprising a third impurity region to which the first voltage is applied, the third well being disposed adjacent to the second well.

Abstract: An electrostatic discharge protection device includes first and second wells of a first conductivity type, the first and second wells having different impurity doping concentrations, respectively, a gate formed on the first well, a source region of a second conductivity type formed at one side of the gate in the first well, a drift region of the second conductivity type formed at the other side of gate and over both of the first well and the second well, and a drain region of the second conductivity type formed in the drift region of the second well.

Abstract: The present invention discloses an electrostatic discharge device for ensuring a pin capacitance using a metal option. The electrostatic discharge device includes an electrostatic discharging unit formed between a power source voltage line and a ground voltage line to discharge static electricity input from a pad. A MOS capacitor of the electrostatic discharge device has a gate terminal connected to the pad via a metal option. A protection unit is formed between the electrostatic discharging unit and the ground voltage line to protect an internal circuit from static electricity stored in the electrostatic discharging unit.

Abstract: An integrated circuit includes an input/output pad for signal exchange with an external circuit, an electrostatic discharge (ESD) protection unit coupled to the input/output pad and configured to form an ESD path between a first voltage line and a second voltage line, a first drive transistor coupled between the first voltage line and the input/output pad, a first driving control unit coupled to a gate of the first drive transistor and configured to control the first drive transistor, a first dummy drive transistor coupled between the first voltage line and the input/output pad, and a first auxiliary driving control unit configured to supply the first voltage to a gate of the first dummy drive transistor in a normal operation mode, and float the gate of the first dummy drive transistor in a non-operation mode in which no power is supplied.

Abstract: A pad part of a semiconductor device includes a semiconductor substrate having a pad forming region; a plurality of dot type stack patterns with a dielectric layer and a conductive layer for option capacitors, formed in the pad forming region and arranged at regular intervals; a first interlayer dielectric formed on the semiconductor substrate to cover the stack patterns; first metal lines formed on the first interlayer dielectric to be connected to the stack patterns arranged in diagonal directions; a second interlayer dielectric formed on the first interlayer dielectric to cover the first metal lines; second metal lines formed on the second interlayer dielectric to be brought into contact with the first metal lines; a pad formed on the second interlayer dielectric; and option metal lines formed on the second interlayer dielectric to connect the second metal lines and the pad to each other.

Abstract: An electrostatic discharge protection device includes a first well comprising a MOS transistor; a second well comprising a first impurity region to which a first voltage is applied, and a second impurity region connected to an input/output pad, the second well being disposed adjacent to the first well; and a third well comprising a third impurity region to which the first voltage is applied, the third well being disposed adjacent to the second well.

Abstract: The present invention discloses an electrostatic discharge device for ensuring a pin capacitance using a metal option. The electrostatic discharge device includes an electrostatic discharging unit formed between a power source voltage line and a ground voltage line to discharge static electricity input from a pad. A MOS capacitor of the electrostatic discharge device has a gate terminal connected to the pad via a metal option. A protection unit is formed between the electrostatic discharging unit and the ground voltage line to protect an internal circuit from static electricity stored in the electrostatic discharging unit.

Abstract: An electrostatic discharge protection element is disclosed for protecting an internal circuit from electrostatic current. The electrostatic discharge protection element forms an embedded LVTSCR by adding a prescribed impurity region within an N-well region having a P-type diode formed therein. A P-well region having a GGNMOS transistor is also formed in the electrostatic discharge protection element. The embedded LVTSCR improves area efficiency, reduces a resistance, and lowers an operational voltage by reducing the distance between the P-type diode and the LVTSCR to allow high-speed operatation.

Abstract: A pad part of a semiconductor device includes a semiconductor substrate having a pad forming region; a plurality of dot type stack patterns with a dielectric layer and a conductive layer for option capacitors, formed in the pad forming region and arranged at regular intervals; a first interlayer dielectric formed on the semiconductor substrate to cover the stack patterns; first metal lines formed on the first interlayer dielectric to be connected to the stack patterns arranged in diagonal directions; a second interlayer dielectric formed on the first interlayer dielectric to cover the first metal lines; second metal lines formed on the second interlayer dielectric to be brought into contact with the first metal lines; a pad formed on the second interlayer dielectric; and option metal lines formed on the second interlayer dielectric to connect the second metal lines and the pad to each other.