Patents by Inventor Dong-ju Yang
Dong-ju Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150108489Abstract: A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Inventors: Joo-Han KIM, Ki-Yong SONG, Dong-Ju YANG, Hee-Joon KIM, Yeo-Geon YOON, Sung-Hen CHO, Chang-Hoon KIM, Jae-Hong KIM, Yu-Gwang JEONG, Ki-Yeup LEE, Sang-Gab KIM, Yun-Jong YEO, Shin-Il CHOI, Ji-Young PARK
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Publication number: 20150053984Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.Type: ApplicationFiled: October 20, 2014Publication date: February 26, 2015Inventors: JEAN-HO SONG, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
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Patent number: 8946004Abstract: A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.Type: GrantFiled: August 19, 2009Date of Patent: February 3, 2015Assignee: Samsung Display Co., Ltd.Inventors: Joo-Han Kim, Ki-Yong Song, Dong-Ju Yang, Hee-Joon Kim, Yeo-Geon Yoon, Sung-Hen Cho, Chang-Hoon Kim, Jae-Hong Kim, Yu-Gwang Jeong, Ki-Yeup Lee, Sang-Gab Kim, Yun-Jong Yeo, Shin-Il Choi, Ji-Young Park
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Patent number: 8865528Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.Type: GrantFiled: July 27, 2010Date of Patent: October 21, 2014Assignee: Samsung Display Co., Ltd.Inventors: Jean-Ho Song, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
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Publication number: 20140209903Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: Samsung Display Co., Ltd.Inventors: Pil-Sang YUN, Ki-Won KIM, Hye-Young RYU, Woo-Geun LEE, Seung-Ha CHOI, Jae-Hyoung YOUN, Kyoung-Jae CHUNG, Young-Wook LEE, Je-Hun LEE, Kap-Soo YOON, Do-Hyun KIM, Dong-Ju YANG, Young-Joo CHOI
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Patent number: 8723179Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.Type: GrantFiled: December 1, 2010Date of Patent: May 13, 2014Assignee: Samsung Display Co., Ltd.Inventors: Pil-Sang Yun, Ki-Won Kim, Hye-Young Ryu, Woo-Geun Lee, Seung-Ha Choi, Jae-Hyoung Youn, Kyoung-Jae Chung, Young-Wook Lee, Je-Hun Lee, Kap-Soo Yoon, Do-Hyun Kim, Dong-Ju Yang, Young-Joo Choi
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Patent number: 8653390Abstract: An engine start/stop switch for a vehicle is provided, including a housing having one end portion exposed outwardly from a dashboard and the other end portion embedded in the dashboard; a button disposed in the housing and having one end portion exposed outwardly to be pressed to start or stop an engine; a slider disposed at the front end of the button to be slid along the inner peripheral surface of the housing; a circuit unit disposed to closely contact the front end of the slider to be electrified when pressed by the slider and to generate an engine start or stop signal; and a coil antenna interposed between the button and the slider to transmit driving waves to the transponder of a portable device carried by a driver. Further, the housing includes first and second housings detachably coupled to each other to encompass the button, slider and circuit unit.Type: GrantFiled: October 14, 2010Date of Patent: February 18, 2014Assignee: ALPS Electric Korea Co., Ltd.Inventors: Woo Young Shim, Dong Ju Yang
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Patent number: 8586990Abstract: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.Type: GrantFiled: August 15, 2011Date of Patent: November 19, 2013Assignee: Samsung Display Co., Ltd.Inventors: Dong-Ju Yang, Yu Gwang Jeong, Ki-Yeup Lee, Sang-Gab Kim, Yun-Jong Yeo, Shin-Il Choi, Hong-Kee Chin, Seung-Ha Choi, Jung-Suk Bang
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Patent number: 8557621Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.Type: GrantFiled: June 10, 2011Date of Patent: October 15, 2013Assignee: Samsung Display Co., Ltd.Inventors: Jong-Hyun Choung, Yang Ho Bae, Jean Ho Song, O Sung Seo, Sun-Young Hong, Hwa Yeul Oh, Bong-Kyun Kim, Nam Seok Suh, Dong-Ju Yang, Wang Woo Lee
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Patent number: 8476123Abstract: A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF6 or SF6/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.Type: GrantFiled: May 17, 2011Date of Patent: July 2, 2013Assignee: Samsung Display Co., Ltd.Inventors: Dong-Ju Yang, Yu-Gwang Jeong, Jean-Ho Song, Ki-Yeup Lee, Shin-Il Choi, Tae-Woo Kim
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Patent number: 8450737Abstract: A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.Type: GrantFiled: May 20, 2010Date of Patent: May 28, 2013Assignee: Samsung Display Co., Ltd.Inventors: Shin-Il Choi, Yu-Gwang Jeong, Ki-Yeup Lee, Dong-Ju Yang, Jean-Ho Song
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Patent number: 8273612Abstract: In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing sufficient nickel to inhibit corrosion during dry etching. The corrosion resistance of the AlNi-containing alloy helps prevent corrosion of the data line, the source electrode, and the drain electrode during selective dry etching that shapes these lines and electrodes.Type: GrantFiled: December 29, 2010Date of Patent: September 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Seok Oh, Yang-Ho Bae, Pil-Sang Yun, Byeong-Beom Kim, Seung-Ha Choi, Sang-Gab Kim, Chang-Ho Jeong, Shin-Il Choi, Hong-Kee Chin, Yu-Gwang Jeong, Dong-Ju Yang
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Publication number: 20120199461Abstract: An engine start/stop switch for a vehicle is provided, including a housing having one end portion exposed outwardly from a dashboard and the other end portion embedded in the dashboard; a button disposed in the housing and having one end portion exposed outwardly to be pressed to start or stop an engine; a slider disposed at the front end of the button to be slid along the inner peripheral surface of the housing; a circuit unit disposed to closely contact the front end of the slider to be electrified when pressed by the slider and to generate an engine start or stop signal; and a coil antenna interposed between the button and the slider to transmit driving waves to the transponder of a portable device carried by a driver. Further, the housing includes first and second housings detachably coupled to each other to encompass the button. slider and circuit unit.Type: ApplicationFiled: October 14, 2010Publication date: August 9, 2012Applicant: ALPS ELECTRIC KOREA CO., LTD.Inventors: Woo Young Shim, Dong Ju Yang
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Patent number: 8211797Abstract: A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate.Type: GrantFiled: October 31, 2008Date of Patent: July 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Ju Yang, Shin-Il Choi, Sang-Gab Kim, Min-Seok Oh, Hong-Kee Chin, Ki-Yeup Lee, Yu-Gwang Jeong, Seung-Ha Choi
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Publication number: 20120135555Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.Type: ApplicationFiled: June 10, 2011Publication date: May 31, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Hyun CHOUNG, Yang Ho BAE, Jean Ho SONG, O. Sung SEO, Sun-Young HONG, Hwa Yeul OH, Bong-Kyun KIM, Nam Seok SUH, Dong-Ju YANG, Wang Woo LEE
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Publication number: 20120064678Abstract: A method for manufacturing a TFT array panel includes forming a photosensitive film pattern with first and second parts in first and second sections on a metal layer, etching the metal layer of a third section using the film pattern as a mask to form first and second metal patterns, etching the film pattern to remove the first part, etching first and second amorphous silicon layers of the third section using the second part as a mask to form an amorphous silicon pattern and a semiconductor, etching the first and second metal patterns of the first section using the second part as a mask to form a source electrode and a drain electrode including an upper layer and a lower layer, and etching the amorphous silicon pattern of the region corresponding to the first section by using the second part as a mask to form an ohmic contact.Type: ApplicationFiled: March 22, 2011Publication date: March 15, 2012Inventors: Byeong-Jin LEE, Yu-Gwang Jeong, Dong-Ju Yang, Bong-Kyun Kim, Hong-Sick Park, Byeong-Beom Kim, Sang-Gab Kim, Ji-Young Park, Jean-Ho Song, Ki-Yeup Lee, Shin-Il Choi
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Publication number: 20120028421Abstract: A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF6 or SF6/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.Type: ApplicationFiled: May 17, 2011Publication date: February 2, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Ju YANG, Yu-Gwang JEONG, Jean-Ho SONG, Ki-Yeup LEE, Shin-Il CHOI, Tae-Woo KIM
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Publication number: 20110297931Abstract: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.Type: ApplicationFiled: August 15, 2011Publication date: December 8, 2011Inventors: Dong-Ju YANG, Yu-Gwang JEONG, Ki-Yeup LEE, Sang-Gab KIM, Yun-Jong YEO, Shin-Il CHOI, Hong-Kee CHIN, Seung-Ha CHOI, Jung-Suk BANG
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Patent number: 8067774Abstract: After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed in a contact hole exposing the signal line during the formation of the contact hole. Accordingly, the contact characteristic between an upper layer including indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) and the signal line may be improved to enhance the adhesion therebetween while not increasing the production cost of the thin film transistor (“TFT”) array panel.Type: GrantFiled: May 4, 2009Date of Patent: November 29, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Ha Choi, Ki-Yeup Lee, Sang-Gab Kim, Shin-il Choi, Dong-Ju Yang, Hong-Kee Chin, Yu-Gwang Jeong, Ji-Young Park, Dong-Hoon Lee, Byeong-Beom Kim
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Patent number: 8017459Abstract: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.Type: GrantFiled: June 12, 2009Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Ju Yang, Yu-Gwang Jeong, Ki-Yeup Lee, Sang-Gab Kim, Yun-Jong Yeo, Shin-Il Choi, Hong-Kee Chin, Seung-Ha Choi, Jung-Suk Bang