Patents by Inventor Dong-Jun Seong
Dong-Jun Seong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11770938Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.Type: GrantFiled: February 3, 2022Date of Patent: September 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Jun Seong, Soon-Oh Park
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Patent number: 11641749Abstract: A semiconductor device includes a first electrode and a first carbon layer on the first electrode. A switch layer is disposed on the first carbon layer and a second carbon layer is disposed on the switch layer. At least one tunneling oxide layer is disposed between the first carbon layer and the second carbon layer. The device further includes a second electrode on the second carbon layer.Type: GrantFiled: May 19, 2021Date of Patent: May 2, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong Jun Seong, Jun Hwan Paik, Hyung Jong Jeong
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Patent number: 11587977Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.Type: GrantFiled: February 11, 2021Date of Patent: February 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Jun Seong, Soon-Oh Park
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Publication number: 20220190034Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.Type: ApplicationFiled: February 3, 2022Publication date: June 16, 2022Inventors: DONG-JUN SEONG, SOON-OH PARK
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Patent number: 11227991Abstract: A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.Type: GrantFiled: June 30, 2020Date of Patent: January 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Jun Seong, Sung-Ho Eun, Soon-Oh Park
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Publication number: 20210273016Abstract: A semiconductor device includes a first electrode and a first carbon layer on the first electrode. A switch layer is disposed on the first carbon layer and a second carbon layer is disposed on the switch layer. At least one tunneling oxide layer is disposed between the first carbon layer and the second carbon layer. The device further includes a second electrode on the second carbon layer.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Dong Jun SEONG, Jun Hwan PAIK, Hyung Jong JEONG
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Publication number: 20210193736Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.Type: ApplicationFiled: February 11, 2021Publication date: June 24, 2021Inventors: DONG-JUN SEONG, SOON-OH PARK
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Patent number: 11037985Abstract: A semiconductor device includes a first electrode and a first carbon layer on the first electrode. A switch layer is disposed on the first carbon layer and a second carbon layer is disposed on the switch layer. At least one tunneling oxide layer is disposed between the first carbon layer and the second carbon layer. The device further includes a second electrode on the second carbon layer.Type: GrantFiled: April 9, 2019Date of Patent: June 15, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong Jun Seong, Jun Hwan Paik, Hyung Jong Jeong
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Patent number: 10957740Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.Type: GrantFiled: June 20, 2019Date of Patent: March 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Jun Seong, Soon-Oh Park
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Publication number: 20200335692Abstract: A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.Type: ApplicationFiled: June 30, 2020Publication date: October 22, 2020Inventors: Dong-Jun SEONG, Sung-Ho EUN, Soon-Oh PARK
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Patent number: 10714685Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.Type: GrantFiled: August 1, 2019Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Min Kyu Yang, Seong Geon Park, Dong Jun Seong, Dong Ho Ahn, Jung Moo Lee, Seol Choi, Hideki Horii
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Patent number: 10692933Abstract: A variable resistance memory device may include a first conductive line, a plurality of stacked structures, and a mold pattern. The first conductive line may be formed on a substrate. The plurality of stacked structures may be formed on the first conductive line, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another. The mold pattern may be formed on the first conductive line to fill a space between the plurality of stacked structures. An upper portion of the mold pattern may include a surface treated layer and a lower portion of the mold pattern may include a non-surface treated layer.Type: GrantFiled: March 20, 2019Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Jun Seong, Yong-Jin Park, Jun-Hwan Paik, Gyu-Hwan Oh
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Publication number: 20200075852Abstract: A semiconductor device includes a first electrode and a first carbon layer on the first electrode. A switch layer is disposed on the first carbon layer and a second carbon layer is disposed on the switch layer. At least one tunneling oxide layer is disposed between the first carbon layer and the second carbon layer. The device further includes a second electrode on the second carbon layer.Type: ApplicationFiled: April 9, 2019Publication date: March 5, 2020Inventors: Dong Jun SEONG, Jun Hwan PAIK, Hyung Jong JEONG
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Publication number: 20200066799Abstract: A variable resistance memory device may include a first conductive line, a plurality of stacked structures, and a mold pattern. The first conductive line may be formed on a substrate. The plurality of stacked structures may be formed on the first conductive line, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another. The mold pattern may be formed on the first conductive line to fill a space between the plurality of stacked structures. An upper portion of the mold pattern may include a surface treated layer and a lower portion of the mold pattern may include a non-surface treated layer.Type: ApplicationFiled: March 20, 2019Publication date: February 27, 2020Inventors: Dong-Jun Seong, Yong-Jin Park, Jun-Hwan Paik, Gyu-Hwan Oh
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Patent number: 10546894Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.Type: GrantFiled: December 20, 2018Date of Patent: January 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Zhe Wu, Dong-ho Ahn, Hideki Horii, Soon-oh Park, Jeong-hee Park, Jin-woo Lee, Dong-jun Seong, Seol Choi
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Publication number: 20190355905Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.Type: ApplicationFiled: August 1, 2019Publication date: November 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Min Kyu YANG, Seong Geon PARK, Dong Jun SEONG, Dong Ho AHN, Jung Moo LEE, Seol CHOI, Hideki HORN
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Publication number: 20190305044Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Inventors: DONG-JUN SEONG, SOON-OH PARK
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Patent number: 10403818Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.Type: GrantFiled: January 9, 2017Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Min Kyu Yang, Seong Geon Park, Dong Jun Seong, Dong Ho Ahn, Jung Moo Lee, Seol Choi, Hideki Horii
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Patent number: 10374008Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.Type: GrantFiled: July 20, 2017Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Jun Seong, Soon-Oh Park
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Publication number: 20190148456Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.Type: ApplicationFiled: December 20, 2018Publication date: May 16, 2019Inventors: Zhe Wu, Dong-ho Ahn, Hideki Horii, Soon-oh Park, Jeong-hee Park, Jin-woo Lee, Dong-jun Seong, Seol Choi