Patents by Inventor Dong-Kak Lee

Dong-Kak Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10685959
    Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Kak Lee, Joon Kim, Bong-hyun Kim, Han-Jin Lim
  • Publication number: 20200075730
    Abstract: A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.
    Type: Application
    Filed: March 14, 2019
    Publication date: March 5, 2020
    Inventors: Dong Kak Lee, Min Woo KIM, Bong Hyun KIM, Hee Young PARK, Seo Jin AHN, Won Yong LEE
  • Publication number: 20200051921
    Abstract: Integrated circuit (IC) devices are provided. An IC device includes a substrate including an active region. The IC device includes a bit line on the substrate. The IC device includes a direct contact connected between the active region and the bit line. The IC device includes a contact plug on the substrate. Moreover, the IC device includes a boron-containing insulating pattern between the contact plug and the direct contact.
    Type: Application
    Filed: March 19, 2019
    Publication date: February 13, 2020
    Inventors: Dong-kak Lee, Yoon-ho Son, Mong-sup Lee, Wook-yeol Yi
  • Publication number: 20190131301
    Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
    Type: Application
    Filed: December 14, 2018
    Publication date: May 2, 2019
    Inventors: Dong-Kak Lee, Joon Kim, Bong-hyun Kim, Han-Jin Lim
  • Publication number: 20160247802
    Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
    Type: Application
    Filed: April 27, 2016
    Publication date: August 25, 2016
    Inventors: Dong-Kak Lee, Joon Kim, Bong-hyun Kim, Han-Jin Lim
  • Patent number: 9349821
    Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Kak Lee, Joon Kim, Bong-hyun Kim, Han-Jin Lim
  • Publication number: 20160071946
    Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
    Type: Application
    Filed: November 13, 2015
    Publication date: March 10, 2016
    Inventors: Dong-Kak Lee, Joon Kim, Bong-hyun Kim, Han-Jin Lim
  • Patent number: 9202813
    Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 1, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-kak Lee, Joon Kim, Bong-hyun Kim, Han-Jin Lim
  • Patent number: 8766355
    Abstract: A semiconductor device includes a device isolation pattern in which a polysilicon layer pattern doped with oxygen, carbon or nitrogen is interposed between an inner wall of a trench and a nitride liner. The semiconductor device includes a semiconductor substrate including a trench, a polysilicon layer pattern on a surface of the trench, a nitride layer pattern on the polysilicon layer pattern, and an insulation layer pattern on the nitride layer pattern and filling the trench. The polysilicon layer pattern may be doped with oxygen, carbon and/or nitrogen. Related manufacturing methods are also disclosed.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kak Lee, Hee-don Hwang
  • Patent number: 8692372
    Abstract: Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kak Lee, Sung-gil Kim, Soo-jin Hong, Sun-ghil Lee, Deok-hyung Lee
  • Patent number: 8354308
    Abstract: A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: January 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-kyu Kang, Gil-heyun Choi, Dae-lok Bae, Byung-lyul Park, Dong-kak Lee
  • Publication number: 20120056263
    Abstract: A semiconductor device includes a device isolation pattern in which a polysilicon layer pattern doped with oxygen, carbon or nitrogen is interposed between an inner wall of a trench and a nitride liner. The semiconductor device includes a semiconductor substrate including a trench, a polysilicon layer pattern on a surface of the trench, a nitride layer pattern on the polysilicon layer pattern, and an insulation layer pattern on the nitride layer pattern and filling the trench. The polysilicon layer pattern may be doped with oxygen, carbon and/or nitrogen. Related manufacturing methods are also disclosed.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 8, 2012
    Inventors: Dong-kak Lee, Hee-don Hwang
  • Publication number: 20120052635
    Abstract: A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.
    Type: Application
    Filed: August 30, 2011
    Publication date: March 1, 2012
    Inventors: Pil-kyu Kang, Gil-heyun Choi, Dae-lok Bae, Byung-Iyul Park, Dong-kak Lee
  • Publication number: 20120001267
    Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
    Type: Application
    Filed: June 27, 2011
    Publication date: January 5, 2012
    Inventors: Dong-kak Lee, Joon Kim, Bong-hyun Kim, Han-Jin Lim
  • Publication number: 20110049596
    Abstract: Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.
    Type: Application
    Filed: March 22, 2010
    Publication date: March 3, 2011
    Inventors: Dong-kak Lee, Sung-gil Kim, Soo-jin Hong, Sun-ghil Lee, Deok-hyung Lee
  • Patent number: 7846836
    Abstract: A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kak Lee, Ki-Hyun Hwang, Jin-Gyun Kim
  • Publication number: 20090280615
    Abstract: A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.
    Type: Application
    Filed: May 4, 2009
    Publication date: November 12, 2009
    Inventors: Dong-Kak LEE, Ki-Hyun HWANG, Jin-Gyun KIM
  • Publication number: 20090179252
    Abstract: A flash memory device may include a lower tunnel insulation layer disposed on a substrate, an upper tunnel insulation layer disposed on the lower tunnel insulation layer, a floating gate disposed on the upper tunnel insulation layer, an intergate insulation layer disposed on the floating gate; and a control gate disposed on the intergate insulation layer.
    Type: Application
    Filed: November 24, 2008
    Publication date: July 16, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-kweon Baek, Sang-ryol Yang, Si-young Choi, Bon-young Koo, Ki-hyun Hwang, Dong-kak Lee
  • Publication number: 20080073690
    Abstract: A flash memory device may include a lower tunnel insulation layer disposed on a substrate, an upper tunnel insulation layer disposed on the lower tunnel insulation layer, a floating gate disposed on the upper tunnel insulation layer, an intergate insulation layer disposed on the floating gate; and a control gate disposed on the intergate insulation layer.
    Type: Application
    Filed: October 31, 2006
    Publication date: March 27, 2008
    Inventors: Sung-kweon Baek, Sang-ryol Yang, Si-young Choi, Bon-young Koo, Ki-hyun Hwang, Dong-kak Lee