Abstract: A non-volatile memory device and a method of manufacturing the same are provided. The device includes a substrate including a cell region and a peripheral region, a gate pattern formed over the substrate in the peripheral region, a multilayered structure formed over the gate pattern in the peripheral region, the multilayered structure including interlayer insulating layers and material layers for sacrificial layers, and a capping layer formed between the gate pattern and the multilayered structure in the peripheral region to cover the substrate, the capping layer configured to prevent diffusion of impurities from the material layers for the sacrificial layers into the substrate in the peripheral region.

Abstract: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.

Abstract: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.

Abstract: Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate.

Abstract: Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate.

Abstract: Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate.

Abstract: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.

Abstract: A 3-dimensional non-volatile memory device, a memory system including the same, and a method of manufacturing the same comprise vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of conductive layers alternately formed along the vertical channel layers, a charge trap layer surrounding the vertical channel layers, the charge trap layer having a smaller thickness in a plurality of first regions, interposed between the plurality of conductive layers and the vertical channel layers, than in a plurality of second regions, interposed between the plurality of interlayer insulating layers and the vertical channel layers and a blocking insulating layer formed in each of the plurality of first regions, between the plurality of conductive layers and the charge trap layer.

Abstract: Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate.

Abstract: A non-volatile memory device and a method of manufacturing the same are provided. The device includes a substrate including a cell region and a peripheral region, a gate pattern formed over the substrate in the peripheral region, a multilayered structure formed over the gate pattern in the peripheral region, the multilayered structure including interlayer insulating layers and material layers for sacrificial layers, and a capping layer formed between the gate pattern and the multilayered structure in the peripheral region to cover the substrate, the capping layer configured to prevent diffusion of impurities from the material layers for the sacrificial layers into the substrate in the peripheral region.

Abstract: A method for fabricating a non-volatile memory device includes forming a channel link layer and an isolation layer surrounding the channel link layer over a substrate, forming a stack structure having interlayer dielectric layers that are alternately stacked with gate electrode layers over the channel link layer and the isolation layer, and forming a pair of channels connected to the channel link layer through the stack structure, and a memory layer interposed between the channel and the stack structure.

Abstract: A 3-dimensional non-volatile memory device, a memory system including the same, and a method of manufacturing the same comprise vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of conductive layers alternately formed along the vertical channel layers, a charge trap layer surrounding the vertical channel layers, the charge trap layer having a smaller thickness in a plurality of first regions, interposed between the plurality of conductive layers and the vertical channel layers, than in a plurality of second regions, interposed between the plurality of interlayer insulating layers and the vertical channel layers and a blocking insulating layer formed in each of the plurality of first regions, between the plurality of conductive layers and the charge trap layer.

Abstract: A method for fabricating a non-volatile memory device includes forming a channel link layer and an isolation layer surrounding the channel link layer over a substrate, forming a stack structure having interlayer dielectric layers that are alternately stacked with gate electrode layers over the channel link layer and the isolation layer, and forming a pair of channels connected to the channel link layer through the stack structure, and a memory layer interposed between the channel and the stack structure.

Abstract: Disclosed herein is a system and method for estimating an Internet-wide transmission path and transmission delay. The system includes indexing construction means configured to function as storage for storing the results of actual measurement of transmission delay for all destinations on the Internet, and configured to, in order to search for necessary actual measurement results using Autonomous System (AS) numbers, translate IP addresses constituting the actual measurement results into AS numbers and index respective path segments with AS numbers, mapping means for mapping the IP addresses of queried two points to AS numbers, AS path estimation means for estimating an AS path between the two AS numbers, and path stitching means for searching for respective path segments constituting the estimated AS path, stitching the found path segments together and stitching IP paths corresponding to the AS path, thereby obtaining a plurality of stitched paths and corresponding transmission delay.

Abstract: A method of fabricating a flash memory device. A DDD ion is implanted into a high voltage PMOS transistor and into source and drain junctions of a cell transistor in order to facilitate a pinch-off phenomenon in the gate to drain overlap region and also increase the number of hot carriers. Accordingly, a program characteristic can be improved, a depletion width between source and drain junctions of a cell can be narrowed and the leakage current can be reduced.

Abstract: A method of fabricating a flash memory device includes defining a high voltage region and a low voltage region on a substrate. The high voltage region provides an area for one or more first transistors configured to operation at a first voltage, the low voltage region providing an area for one or more second transistors configured to operation at a second voltage that is lower than the first voltage, each first transistor having a gate and a source/drain region on each side of the gate. A first impurity region is formed as part of the source/drain region, the first impurity region having a first depth from an upper surface of the substrate, the first impurity region being of first conductivity having a first impurity concentration.

Abstract: A method of manufacturing a high voltage device includes forming a junction region in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A portion of the insulating layer is etched so that the junction region is exposed. Arsenic is implanted into the exposed junction region to form plug ion implantation regions. A plug is formed on the plug ion implantation regions into which arsenic has been implanted.

Abstract: A method of manufacturing a high-voltage device DDD (Double Doped Drain) ion implantation process is performed at a tilt angle in order to form a smooth junction profile. Accordingly, the intensity of an electric field can be reduced and breakdown voltage margin can be secured.

Abstract: The present invention relates to anti-obesity polypeptides for restraining the generation of adipose tissue in vivo. The anti-obesity polypeptides can be used as obesity preventive vaccines or treating agents and in curing diabetes.

Abstract: Provided is a high voltage transistor in a flash memory device comprising: a source/drain junction of a DDD structure consisting of a high-concentration impurity region and a low-concentration impurity region surrounding the high-concentration impurity region, the high-concentration impurity region being formed in parallel with a gate electrode at a distance spaced by a location in which a contact hole is formed, and having a rectangular shape whose width is the same as or wider than that of the contact hole and whose length is the same as or narrower than that of an active region through which the gate electrode passes. Accordingly, a current density to pass the gate electrode neighboring the contact hole portion and a current density to pass the gate electrode at a portion where the contact hole cannot be formed become uniform. A uniform and constant saturation current can be obtained regardless of the number of the contact hole.