Abstract: A storage device includes a volatile memory and a storage controller, which is configured to control the volatile memory. The volatile memory includes a memory cell array, which has a plurality of sub-cell arrays therein, and a plurality of sub-wordline driver blocks, which are configured to drive sub-wordlines electrically connected to at least one of the plurality of sub-cell arrays.

Abstract: A storage device includes a volatile memory and a storage controller, which is configured to control the volatile memory. The volatile memory includes a memory cell array, which has a plurality of sub-cell arrays therein, and a plurality of sub-wordline driver blocks, which are configured to drive sub-wordlines electrically connected to at least one of the plurality of sub-cell arrays.

Abstract: A method of operating a storage device includes: periodically performing a patrol read operation on a memory device; storing failure information according to the patrol read operation in a buffer memory; generating an uncorrectable error as a result of a first error correction operation performed on read data of the memory device; loading the failure information from the buffer memory; and performing a second error correction operation on the read data by using the failure information.

Abstract: An electronic device includes: a memory device; a nonvolatile memory configured to store a plurality of first configuration parameters respectively corresponding to operating voltages of the memory device and a plurality of second configuration parameters respectively corresponding to operating temperatures of the memory device; and a memory controller configured to: determine a value of a third configuration parameter corresponding to an operating voltage of the memory device among the plurality of first configuration parameters stored in the nonvolatile memory without performing a training operation, determine a value of a fourth configuration parameter corresponding to an operating temperature of the memory device among the plurality of second configuration parameters stored in the nonvolatile memory without performing the training operation, and drive the memory device according to the determined values of the third and the fourth configuration parameters.

Abstract: A storage device includes a non-volatile memory; a volatile memory; and a memory controller configured to control the non-volatile memory and the volatile memory. The memory controller is configured to, in response to a determination that a progressive defect has occurred in at least one memory of the non-volatile memory or the volatile memory during an operation of the storage device, such that the at least one memory is determined to be a defective memory, perform a repair operation on the defective memory based on executing a memory revival firmware.

Abstract: A test operation condition of a volatile memory device is set such that an error probability is increased based on the test operation condition, compared to a normal operation condition for a normal operation of the volatile memory device. A test mode is set with respect to a test object region corresponding to at least a portion of a memory cell array included in the volatile memory device. A test operation of the volatile memory device is performed based on the test operation condition during the test mode to detect error position information of errors in data stored in the test object region. A runtime repair operation is performed with respect to the volatile memory device based on the error position information.

Abstract: A storage device including a nonvolatile memory device, a dynamic random access memory (DRAM) device, and a storage controller, an operation method of the storage device including performing an access operation on the DRAM device, collecting accumulated error information about the DRAM device based on the access operation, detecting a fail row of the DRAM device based on the accumulated error information, and performing a runtime repair operation on the detected fail row.

Abstract: A method of controlling repair of a volatile memory device, includes, performing a patrol read operation repeatedly to provide error position information of errors included in read data from a volatile memory device, generating accumulated error information by accumulating the error position information based on the patrol read operation performed repeatedly, determining error attribute based on the accumulated error information, the error attribute indicating correlation between the errors and a structure of the volatile memory device, and performing a runtime repair operation with respect to the volatile memory device based on the accumulated error information and the error attribute. The errors may be managed efficiently to prevent failure of the volatile memory device, and thus performance and lifetime of the volatile memory device and the storage device may be enhanced.

Abstract: A memory system includes a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup region, and a memory controller configured to store data to be stored in a plurality of selected memory cells in the plurality of selected memory cells and the backup region, the plurality of selected memory cells being connected to a selected word line of a selected memory device among the plurality of memory devices, and replace the selected word line with a redundancy word line to which a plurality of redundancy memory cells among the plurality of memory cells are connected in response to a correctable error correction code (CECC) occurring in at least one of the plurality of selected memory cells.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit connected between the memory cell array and the ECC engine, an error information register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The control logic circuit controls the ECC engine, the I/O gating circuit and the error information register based on a command and address. The I/O gating circuit provides the ECC engine with codewords which are read from the memory cell array through refresh operations on the plurality of memory cell rows. The ECC engine performs an ECC decoding on main data of the codewords based on parity bits of the codewords and provides error generation signals to the control logic circuit in response to detecting correctable errors with respect to a corresponding address resulting from performing the ECC decoding.

Abstract: A storage device includes a non-volatile memory; a volatile memory; and a memory controller configured to control the non-volatile memory and the volatile memory. The memory controller is configured to, in response to a determination that a progressive defect has occurred in at least one memory of the non-volatile memory or the volatile memory during an operation of the storage device, such that the at least one memory is determined to be a defective memory, perform a repair operation on the defective memory based on executing a memory revival firmware.

Abstract: An electronic device includes: a memory device; a nonvolatile memory configured to store a plurality of first configuration parameters respectively corresponding to operating voltages of the memory device and a plurality of second configuration parameters respectively corresponding to operating temperatures of the memory device; and a memory controller configured to: determine a value of a third configuration parameter corresponding to an operating voltage of the memory device among the plurality of first configuration parameters stored in the nonvolatile memory without performing a training operation, determine a value of a fourth configuration parameter corresponding to an operating temperature of the memory device among the plurality of second configuration parameters stored in the nonvolatile memory without performing the training operation, and drive the memory device according to the determined values of the third and the fourth configuration parameters.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit connected between the memory cell array and the ECC engine, an error information register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The control logic circuit controls the ECC engine, the I/O gating circuit and the error information register based on a command and address. The I/O gating circuit provides the ECC engine with codewords which are read from the memory cell array through refresh operations on the plurality of memory cell rows. The ECC engine performs an ECC decoding on main data of the codewords based on parity bits of the codewords and provides error generation signals to the control logic circuit in response to detecting correctable errors with respect to a corresponding address resulting from performing the ECC decoding.

Abstract: A test operation condition of a volatile memory device is set such that an error probability is increased based on the test operation condition, compared to a normal operation condition for a normal operation of the volatile memory device. A test mode is set with respect to a test object region corresponding to at least a portion of a memory cell array included in the volatile memory device. A test operation of the volatile memory device is performed based on the test operation condition during the test mode to detect error position information of errors in data stored in the test object region. A runtime repair operation is performed with respect to the volatile memory device based on the error position information.

Abstract: A method of controlling repair of a volatile memory device, includes, performing a patrol read operation repeatedly to provide error position information of errors included in read data from a volatile memory device, generating accumulated error information by accumulating the error position information based on the patrol read operation performed repeatedly, determining error attribute based on the accumulated error information, the error attribute indicating correlation between the errors and a structure of the volatile memory device, and performing a runtime repair operation with respect to the volatile memory device based on the accumulated error information and the error attribute. The errors may be managed efficiently to prevent failure of the volatile memory device, and thus performance and lifetime of the volatile memory device and the storage device may be enhanced.

Abstract: A memory system includes a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup region, and a memory controller configured to store data to be stored in a plurality of selected memory cells in the plurality of selected memory cells and the backup region, the plurality of selected memory cells being connected to a selected word line of a selected memory device among the plurality of memory devices, and replace the selected word line with a redundancy word line to which a plurality of redundancy memory cells among the plurality of memory cells are connected in response to a correctable error correction code (CECC) occurring in at least one of the plurality of selected memory cells.

Abstract: A storage device including a nonvolatile memory device, a dynamic random access memory (DRAM) device, and a storage controller, an operation method of the storage device including performing an access operation on the DRAM device, collecting accumulated error information about the DRAM device based on the access operation, detecting a fail row of the DRAM device based on the accumulated error information, and performing a runtime repair operation on the detected fail row.

Abstract: A method of operating a storage controller which is included in a data storage device and initializes at least one main memory of the data storage device includes: transmitting, by a processor of the storage controller, a first indication signal for indicating initialization of the main memory of the data storage device to a first memory initialization device; generating, by a register of the first memory initialization device, a selection signal corresponding to the first indication signal, and outputting, by a memory set of the first memory initialization device, a first initialization signal to the main memory in response to the selection signal to initialize the main memory.

Abstract: Techniques are described herein for reducing the number of inputs required by a user to utilize copied/cut content to perform various operations. In various implementations, it may be determined that new content has been added to a pasteboard data structure stored in memory of a computing device. The new content may be ready to be provided as input to one or more applications in response to a paste command. The new content may be analyzed to identify attribute(s) of the new content. Additionally or alternatively, dynamic attribute(s) of a state of the computing device may be identified. In various implementations, based on the attribute(s) of the new content and/or the dynamic attribute(s), candidate action(s) may be identified that are performable using the new content as input. Output may be generated and provided that is based the candidate action(s).

Abstract: A storage device is provided. The storage device includes storage clusters, and a controller. The controller receives a command and an address from an external host device, selects a storage cluster according to the received address, and transmits the received command and the received address to the selected storage cluster. The controller controls the storage clusters as normal storage clusters and slow storage clusters according to a temperature of a zone to which the storage clusters belong.