Abstract: A power provider includes: a first power converter to convert an input voltage, and output a first power voltage to a display panel through a first power line; a second power converter to convert the input voltage, and output a second power voltage to the display panel through a second power line; and a short circuit detecting circuit to detect a short-circuit of the first power line and the second power line in the display panel, by determining whether or not a level of a sensed voltage measured at the second power line is greater than or equal to a reference short circuit voltage level during a short circuit detecting period. The short circuit detecting circuit is to vary a length of the short circuit detecting period and the reference short circuit voltage level in response to a driving frequency.

Abstract: A voltage converter includes an input voltage line; an inductor coupled to the input voltage line; transistors coupled to the inductor; an output voltage line coupled to at least one of the transistors; a current sensor coupled to at least one of the input voltage line, the inductor, or the output voltage line; and a comparator coupled between the current sensor and the transistors. A DC-DC converter may include a voltage converter having an inductor and a plurality of transistors and configured to convert an input voltage into a power voltage and output the power voltage to an output terminal, an input current sensor configured to sense the input current of the converter, and a controller configured to change the slew rate of an inductor voltage in response to the input current of the converter and a preset reference current.

Abstract: A power provider includes: a first power converter to convert an input voltage, and output a first power voltage to a display panel through a first power line; a second power converter to convert the input voltage, and output a second power voltage to the display panel through a second power line; and a short circuit detecting circuit to detect a short-circuit of the first power line and the second power line in the display panel, by determining whether or not a level of a sensed voltage measured at the second power line is greater than or equal to a reference short circuit voltage level during a short circuit detecting period. The short circuit detecting circuit is to vary a length of the short circuit detecting period and the reference short circuit voltage level in response to a driving frequency.

Abstract: A voltage converter includes an input voltage line; an inductor coupled to the input voltage line; transistors coupled to the inductor; an output voltage line coupled to at least one of the transistors; a current sensor coupled to at least one of the input voltage line, the inductor, or the output voltage line; and a comparator coupled between the current sensor and the transistors. A DC-DC converter may include a voltage converter having an inductor and a plurality of transistors and configured to convert an input voltage into a power voltage and output the power voltage to an output terminal, an input current sensor configured to sense the input current of the converter, and a controller configured to change the slew rate of an inductor voltage in response to the input current of the converter and a preset reference current.

Abstract: A display device and an operating method of the display device are provided. The display device may include: a first transistor controlled by a first control signal to connect an input terminal to which an input voltage is applied and a first node; a second transistor controlled by a second control signal to connect a second node to which a power supply voltage is outputted and the first node; an overcharge recognition circuit configured to receive a first reference voltage, a feedback voltage, and a second reference voltage, to determine whether it is overcharged, and to output an overcharge recognition signal; and a discharge circuit configured to provide a first discharge path for discharging the power supply voltage based on an enable signal generated depending on the overcharge recognition signal.

Abstract: A display device and an operating method of the display device are provided. The display device may include: a first transistor controlled by a first control signal to connect an input terminal to which an input voltage is applied and a first node; a second transistor controlled by a second control signal to connect a second node to which a power supply voltage is outputted and the first node; an overcharge recognition circuit configured to receive a first reference voltage, a feedback voltage, and a second reference voltage, to determine whether it is overcharged, and to output an overcharge recognition signal; and a discharge circuit configured to provide a first discharge path for discharging the power supply voltage based on an enable signal generated depending on the overcharge recognition signal.

Abstract: A display device includes the following elements: a display panel comprising pixels; a data driver supplying data signals to the plurality of pixels; a driving voltage supply supplying a first driving voltage to the data driver; a power supply supplying a first input driving voltage to the driving voltage supply; and a timing controller providing control signals to the data driver, the driving voltage supply, and the power supply and providing luminance information and per-second frame rate information of the display panel to the driving voltage supply. The driving voltage supply comprises an input driving voltage adjuster which adjusts the first input driving voltage to a second input driving voltage based on the luminance information and the per-second frame rate information.

Abstract: A display device includes the following elements: a display panel comprising pixels; a data driver supplying data signals to the plurality of pixels; a driving voltage supply supplying a first driving voltage to the data driver; a power supply supplying a first input driving voltage to the driving voltage supply; and a timing controller providing control signals to the data driver, the driving voltage supply, and the power supply and providing luminance information and per-second frame rate information of the display panel to the driving voltage supply. The driving voltage supply comprises an input driving voltage adjuster which adjusts the first input driving voltage to a second input driving voltage based on the luminance information and the per-second frame rate information.

Abstract: A voltage converter includes an input voltage line; an inductor coupled to the input voltage line; transistors coupled to the inductor; an output voltage line coupled to at least one of the transistors; a current sensor coupled to at least one of the input voltage line, the inductor, or the output voltage line; and a comparator coupled between the current sensor and the transistors. A DC-DC converter may include a voltage converter having an inductor and a plurality of transistors and configured to convert an input voltage into a power voltage and output the power voltage to an output terminal, an input current sensor configured to sense the input current of the converter, and a controller configured to change the slew rate of an inductor voltage in response to the input current of the converter and a preset reference current.

Abstract: A repair information providing device in an integrated circuit including a plurality of memory blocks includes a plurality of faulty cell address registers connected to the memory blocks, respectively, a repair information storage block configured to store repair information including an address of a faulty cell and a memory index indicating a memory block having the faulty cell, a repair information control block configured to read the repair information from the repair information storage block, transfer the address of the faulty cell included in the repair information to the respective faulty cell address registers, and generate a memory block selection signal based on the memory index included in the repair information, and a clock gating block configured to receive a clock signal, and selectively transfer the clock signal to one of the faulty cell address registers connected to the memory block having the faulty cell in response to receiving the memory block selection signal.

Abstract: A system on chip (SOC) is provided. The system on chip (SOC) includes: at least one core including a plurality of scan chains operated by a trigger signal; a delay controller generating a delay target selection signal selecting at least one of the plurality of scan chains and a delay depth control signal indicating a delay depth of the trigger signal; and a delay signal generating unit delaying the trigger signal based on the delay target selection signal and the delay depth control signal and providing the delayed trigger signal to the plurality of scan chains.

Abstract: A repair information providing device in an integrated circuit including a plurality of memory blocks includes a plurality of faulty cell address registers connected to the memory blocks, respectively, a repair information storage block configured to store repair information including an address of a faulty cell and a memory index indicating a memory block having the faulty cell, a repair information control block configured to read the repair information from the repair information storage block, transfer the address of the faulty cell included in the repair information to the respective faulty cell address registers, and generate a memory block selection signal based on the memory index included in the repair information, and a clock gating block configured to receive a clock signal, and selectively transfer the clock signal to one of the faulty cell address registers connected to the memory block having the faulty cell in response to receiving the memory block selection signal.

Abstract: A system on chip (SOC) is provided. The system on chip (SOC) includes: at least one core including a plurality of scan chains operated by a trigger signal; a delay controller generating a delay target selection signal selecting at least one of the plurality of scan chains and a delay depth control signal indicating a delay depth of the trigger signal; and a delay signal generating unit delaying the trigger signal based on the delay target selection signal and the delay depth control signal and providing the delayed trigger signal to the plurality of scan chains.

Abstract: A method of testing a plurality of DUTs includes providing a plurality of shift registers to test a plurality of cores in each DUT, supplying test input data, a test mode input signal, a test clock signal, and a test reset signal to the shift registers and cores, receiving a master bit, a first control value, and a second control value, based on the test input data and the test mode input signal, according to the test clock signal and the test reset signal, selecting at least one core and a test method, according to the first control value, selecting a target DUT according to the master bit or the second control value, simultaneously testing and debugging the selected core according to the test method, and outputting the test data output of the target DUT to check a result of the testing when an output enable signal is received.

Abstract: A method of testing a plurality of DUTs includes providing a plurality of shift registers to test a plurality of cores in each DUT, supplying test input data, a test mode input signal, a test clock signal, and a test reset signal to the shift registers and cores, receiving a master bit, a first control value, and a second control value, based on the test input data and the test mode input signal, according to the test clock signal and the test reset signal, selecting at least one core and a test method, according to the first control value, selecting a target DUT according to the master bit or the second control value, simultaneously testing and debugging the selected core according to the test method, and outputting the test data output of the target DUT to check a result of the testing when an output enable signal is received.

Abstract: A scan based Automatic Test Pattern Generation (ATPG) test circuit, a test method using the test method, and a scan chain reordering method are disclosed. The test circuit tests for scan chains comprising unknown values which could adversely influence a test result. The test circuit uses a scan test point circuit to prevent unknown values from propagating through the test circuit, thus keeping the unknown values from influencing the test result. The reordering method is used where two scan chains comprising an unknown value exist in a single scan cycle so that the unknown values can be located during different clock cycles.

Abstract: A scan based Automatic Test Pattern Generation (ATPG) test circuit, a test method using the test method, and a scan chain reordering method are disclosed. The test circuit tests for scan chains comprising unknown values which could adversely influence a test result. The test circuit uses a scan test point circuit to prevent unknown values from propagating through the test circuit, thus keeping the unknown values from influencing the test result. The reordering method is used where two scan chains comprising an unknown value exist in a single scan cycle so that the unknown values can be located during different clock cycles.

Abstract: A system on chip and method of testing and/or debugging the same, where the system on chip includes a plurality of circuits and a control circuit for receiving a serial-parallel mode control signal and at least one selection signal externally input from one or more of a plurality of pins and outputting an output signal depending on values of the serial-parallel mode control signal and the at least one selection signal.

Abstract: A system on chip and method of testing and/or debugging the same, where the system on chip includes a plurality of circuits and a control circuit for receiving a serial-parallel mode control signal and at least one selection signal externally input from one or more of a plurality of pins and outputting an output signal depending on values of the serial-parallel mode control signal and the at least one selection signal.