Patents by Inventor Dong Kwan Suh

Dong Kwan Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11568323
    Abstract: Disclosed is an electronic device. The An electronic device including a storage, and a processor configured to perform convolution processing on target data and kernel data based on stride information that indicates an interval at which the kernel data is applied to the target data stored in the storage, in which the processor is further configured to divide the target data into a plurality of pieces of sub-data based on first stride information, perform the convolution processing on the plurality of pieces of sub-data and a plurality of pieces of sub-kernel data respectively corresponding to the plurality of pieces of sub-data based on second stride information that is different from the first stride information, and combine a plurality of processing results, the plurality of pieces of sub-kernel data are obtained by dividing the kernel data based on the first stride information, and the second stride information indicates that the interval at which the kernel data is applied to the target data is 1.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: January 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-hoon Kim, Young-hwan Park, Dong-kwan Suh, Keshava Prasad Nagaraja, Dae-hyun Kim, Suk-jin Kim, Han-su Cho, Hyun-jung Kim
  • Publication number: 20220386607
    Abstract: The present invention relates to a novel nicotinamide compound, a method for preparing the same, and a herbicide comprising the compound. The compound of the present invention is useful as a herbicide for foliar treatment or soil treatment because it has high safety for wheat or corn and has excellent herbicidal activity against grassy weeds, sedge weeds or broadleaf weeds.
    Type: Application
    Filed: October 21, 2020
    Publication date: December 8, 2022
    Inventors: Young Kwan KO, Eun Ae KIM, Ill Young LEE, Hee Nam LIM, Jung Sub CHOI, Jee Hee SUH, Nack Jeong KIM, Dong Wan KOO, Hyun Jin KIM, Gyu Hwan YON, Jae Deok KIM, Seungae OH, So-Young LEE, Chan Yong PARK, Yun Kyoung HWANG, Byung Hoon AHN, Ah Reum KIM, Hye Ji HAN, Sungjun PARK, Junhyuk CHOI, Jisoo LIM, Mi Sook HONG
  • Patent number: 11263018
    Abstract: A vector processor is disclosed. The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data (SIMD) lanes, storing each of a plurality of pieces of data, and respectively outputting input data to be used in a current cycle among the plurality of pieces of data, a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files, and performing shuffling such that the received plurality of pieces of input data respectively correspond to the plurality of SIMD lanes and outputting the same; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-seok Kwon, Jae-un Park, Dong-kwan Suh, Kang-jin Yoon
  • Patent number: 11093439
    Abstract: A processor for performing deep learning is provided herein. The processor includes a processing element unit including a plurality of processing elements arranged in a matrix form including a first row of processing elements and a second row of processing elements. The processing elements are fed with filter data by a first data input unit which is connected to the first row processing elements. A second data input unit feeds target data to the processing elements. A shifter composed of registers feeds instructions to the processing elements. A controller in the processor controls the processing elements, the first data input unit and second data input unit to process the filter data and target data, thus providing sum of products (convolution) functionality.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-hoon Kim, Young-hwan Park, Dong-kwan Suh, Keshava prasad Nagaraja, Suk-jin Kim, Han-su Cho, Hyun-jung Kim
  • Patent number: 10782974
    Abstract: A VLIW (Very Long Instruction Word) interface device includes a memory configured to store instructions and data, and a processor configured to process the instructions and the data, wherein the processor includes an instruction fetcher configured to output an instruction fetch request to load the instruction from the memory, a decoder configured to decode the instruction loaded on the instruction fetcher, an arithmetic logic unit (ALU) configured to perform an operation function if the decoded instruction is an operation instruction, a memory interface scheduler configured to schedule the instruction fetch request or a data fetch request that is input from the arithmetic logic unit, and a memory operator configured to perform a memory access operation in accordance with the scheduled instruction fetch request or data fetch request.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-chul Cho, Suk-jin Kim, Chul-soo Park, Dong-kwan Suh
  • Publication number: 20200272478
    Abstract: A vector processor is disclosed. The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data (SIMD) lanes, storing each of a plurality of pieces of data, and respectively outputting input data to be used in a current cycle among the plurality of pieces of data, a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files, and performing shuffling such that the received plurality of pieces of input data respectively correspond to the plurality of SIMD lanes and outputting the same; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit.
    Type: Application
    Filed: October 23, 2017
    Publication date: August 27, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-seok KWON, Jae-un PARK, Dong-kwan SUH, Kang-jin YOON
  • Publication number: 20200272946
    Abstract: Disclosed is an electronic device. The An electronic device including a storage, and a processor configured to perform convolution processing on target data and kernel data based on stride information that indicates an interval at which the kernel data is applied to the target data stored in the storage, in which the processor is further configured to divide the target data into a plurality of pieces of sub-data based on first stride information, perform the convolution processing on the plurality of pieces of sub-data and a plurality of pieces of sub-kernel data respectively corresponding to the plurality of pieces of sub-data based on second stride information that is different from the first stride information, and combine a plurality of processing results, the plurality of pieces of sub-kernel data are obtained by dividing the kernel data based on the first stride information, and the second stride information indicates that the interval at which the kernel data is applied to the target data is 1.
    Type: Application
    Filed: May 16, 2018
    Publication date: August 27, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-hoon KIM, Young-hwan PARK, Dong-kwan SUH, Keshava Prasad NAGARAJA, Dae-hyun KIM, Suk-jin KIM, Han-su CHO, Hyun-jung KIM
  • Patent number: 10606594
    Abstract: A method of executing, by a processor, a multi-thread including threads of the processor, includes setting a mask value indicating execution of one of the threads of the processor based on an instruction, setting an inverted mask value based on the set mask value; and executing the thread of the processor based on the set mask value and the set inverted mask value.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-seok Lee, Dong-kwan Suh, Seung-won Lee
  • Patent number: 10599439
    Abstract: Provided are a method and apparatus for processing a very long instruction word (VLIW) instruction. The method includes acquiring a calculation allocation instruction including information regarding whether the VLIW instructions are allocated to a plurality of slots; updating a database including the information regarding whether the VLIW instructions are allocated to the plurality of slots based on the acquired calculation allocation instruction; and allocating at least one VLIW instruction to each of the plurality of slots based on the updated database.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-kwan Suh, Suk-jin Kim, Do-hyung Kim, Tai-song Jin
  • Patent number: 10565017
    Abstract: A multi-thread processor and a method of controlling a multi-thread processor are provided. The multi-thread processor includes at least one functional unit; a mode register; and a controller configured to control the mode register to store thread mode information corresponding to a task to be processed among a plurality of thread modes, wherein the plurality of thread modes are divided based on a size and a number of at least one thread that is concurrently processed in one of the at least one functional unit, allocate at least one thread included in the task to the at least one functional unit based on the thread mode information stored in the mode register and control the at least one functional unit to process the at least one thread.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kwan Suh, Suk-jin Kim, Jin-sae Jung, Kang-jin Yoon
  • Patent number: 10481867
    Abstract: A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: November 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-un Park, Jong-hun Lee, Ki-seok Kwon, Dong-kwan Suh, Kang-jin Yoon, Jung-uk Cho
  • Patent number: 10409596
    Abstract: Disclosed is an apparatus comprising: a plurality of memory banks; and a controller for generating a plurality of lookup tables storing data, needed for vector arithmetic operations, copied from data stored in the plurality of memory banks, and generating vector data by reading the data in the generated lookup tables.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-uk Cho, Suk-jin Kim, Dong-kwan Suh
  • Patent number: 10396797
    Abstract: Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kwan Suh, Ki-seok Kwon, Young-hwan Park, Seung-won Lee, Suk-jin Kim
  • Patent number: 10318452
    Abstract: A processor and a control method thereof are processed. The processor includes an instruction fetch module configured to receive a first instruction of an interrupt service routine without backup of data stored in a register in response to processing of the interrupt service routine being requested, a detecting module configured to analyze the received first instruction to determine whether the data stored in the register needs to be changed, an instruction generating module configured to generate a second instruction for storing data in a temporary memory when the stored data is initially changed, an instruction selecting module configured to sequentially select the generated second instruction and first instruction; and a control module configured to perform the second instruction and the first instruction.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chae-seok Im, Dong-kwan Suh, Suk-jin Kim, Seung-won Lee
  • Publication number: 20190147319
    Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network. The apparatus may include a memory, and a processor configured to read, from the memory, one of divided blocks of input data stored in a memory; generate an output block by performing the convolution operation on the one of the divided blocks with a kernel; generate a feature map by using the output block, and write the feature map to the memory.
    Type: Application
    Filed: October 18, 2018
    Publication date: May 16, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-hoon KIM, Young-hwan PARK, Dong-kwan SUH, Keshava PRASAD, Dae-hyun KIM, Suk-jin KIM, Han-su CHO, Hyun-jung KIM
  • Publication number: 20190129885
    Abstract: A processor for performing deep learning is provided herein. The processor includes a processing element unit including a plurality of processing elements arranged in a matrix form including a first row of processing elements and a second row of processing elements. The processing elements are fed with filter data by a first data input unit which is connected to the first row processing elements. A second data input unit feeds target data to the processing elements. A shifter composed of registers feeds instructions to the processing elements. A controller in the processor controls the processing elements, the first data input unit and second data input unit to process the filter data and target data, thus providing sum of products (convolution) functionality.
    Type: Application
    Filed: September 27, 2018
    Publication date: May 2, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-hoon KIM, Young-hwan PARK, Dong-kwan SUH, Keshava PRASAD NAGARAJA, Suk-jin KIM, Han-su CHO, Hyun-jung KIM
  • Publication number: 20190114542
    Abstract: An electronic apparatus and method thereof are provided for performing deep learning. The electronic apparatus includes a storage configured to store target data and kernel data; and a processor including a plurality of processing elements that are arranged in a matrix shape. The processor is configured to input, to each of the plurality of processing elements, a first non-zero element from among a plurality of first elements included in the target data, and sequentially input, to each of a plurality of first processing elements included in a first row from among the plurality of processing elements, a second non-zero element from among the plurality of elements included in the kernel data. Each of the plurality of first processing elements is configured to perform an operation between the input first non-zero element and the input second non-zero element, based on depth information of the first non-zero element and depth information of the second non-zero element.
    Type: Application
    Filed: July 10, 2018
    Publication date: April 18, 2019
    Inventors: Kyoung-hoon Kim, Young-hwan Park, Dong-kwan Suh, Keshava Prasad Nagaraja, Dae-hyun Kim, Suk-jin Kim, Han-su Cho, Hyun-jung Kim
  • Patent number: 10013176
    Abstract: Methods and apparatuses for parallel processing data are disclosed. One method includes reading items of data from a memory using at least memory access address, confirming items of data with the same memory address among the read items of data, and masking the confirmed items of data other than one of the confirmed items of data. A correction value is generated for the memory access address using the confirmed items of data, and an operation is performed on data that has not been masked using the confirmed items of data and the correction value. Data obtained by operating on the data that has not been masked is stored as at least on representative data item for the data items with the same memory address. A schedule of a compiler of a processor is adjusted by performing bypassing of memory access address alias checking for at least one memory access address.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: July 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-kwan Suh, Suk-jin Kim, Young-hwan Park
  • Publication number: 20180101357
    Abstract: A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.
    Type: Application
    Filed: October 6, 2017
    Publication date: April 12, 2018
    Inventors: Jae-un PARK, Jong-hun LEE, Ki-seok KWON, Dong-kwan SUH, Kang-jin YOON, Jung-uk CHO
  • Publication number: 20180088998
    Abstract: A multi-thread processor and a method of controlling a multi-thread processor are provided. The multi-thread processor includes at least one functional unit; a mode register; and a controller configured to control the mode register to store thread mode information corresponding to a task to be processed among a plurality of thread modes, wherein the plurality of thread modes are divided based on a size and a number of at least one thread that is concurrently processed in one of the at least one functional unit, allocate at least one thread included in the task to the at least one functional unit based on the thread mode information stored in the mode register and control the at least one functional unit to process the at least one thread.
    Type: Application
    Filed: August 4, 2017
    Publication date: March 29, 2018
    Inventors: Dong-kwan SUH, Suk-jin KIM, Jin-sae JUNG, Kang-jin YOON