Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device may include: a substrate comprising an active pattern; a source/drain pattern on the active pattern; a device isolation layer at a lateral side of the active pattern; a lower power structure below a top surface of the substrate; a lower contact penetrating the device isolation layer and connecting the source/drain pattern to the lower power structure; and a power delivery network layer below the top surface of the substrate, wherein the lower power structure comprises a connecting portion connected to the lower contact, and wherein the lower contact comprises a protruding portion buried in the connecting portion.

Abstract: A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.

Abstract: A semiconductor device includes a substrate, a first active pattern that includes a first side wall and a second side wall opposite to the first side wall in a second horizontal direction, a first insulating structure in a first trench extending in the first horizontal direction on the first side wall of the first active pattern, a second insulating structure in a second trench extending in the first horizontal direction on the second side of the first active pattern, and includes a first insulating layer on side walls and a bottom surface of the second trench, and a second insulating layer in the second trench on the first insulating layer, a gate-cut extending in the first horizontal direction on the first insulating structure, and a gate electrode extending in the second horizontal direction on the first active pattern.

Abstract: The semiconductor device including an active pattern on a substrate and extending in a first direction, a gate structure on the active pattern, including a gate electrode extending in a second direction different from the first direction, a source/drain pattern on at least one side of the gate structure, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern, wherein with respect to an upper surface of the active pattern, a height of an upper surface of the gate electrode is same as a height of an upper surface of the source/drain contact, and the source/drain contact comprises a lower source/drain contact and an upper source/drain contact on the lower source/drain contact, may be provided.

Abstract: A semiconductor device includes a substrate, an active pattern disposed on the substrate and that extends in a first horizontal direction, a field insulating layer disposed on the substrate and that surrounds a sidewall of the active pattern, a gate electrode disposed on the field insulating layer and that extends in a second horizontal direction, a source/drain region disposed on a side of the gate electrode, a first interlayer insulating layer disposed on the field insulating layer and that surrounds a portion of a sidewall of the source/drain region, a second interlayer insulating layer disposed on the first interlayer insulating layer and that surrounds a sidewall of the gate electrode, and a source/drain contact that penetrates through the second interlayer insulating layer and is electrically connected to the source/drain region. The source/drain contact includes a skirt that protrudes from a lower sidewall toward the second interlayer insulating.

Abstract: A semiconductor device includes: a substrate; an active pattern and a field insulating layer surrounding a sidewall of the active pattern on the substrate; first and second gate electrodes on the active pattern and extending in a direction different from that of the active pattern; an interlayer insulating layer surrounding a sidewall of each of the first and second gate electrodes; a gate spacer on opposing sidewalls of each of the first and second gate electrodes that includes a first sidewall and a second sidewall opposite the first sidewall in the first horizontal direction, each of which contacts the interlayer insulating layer; and a first gate cut dividing the second gate electrode into two portions, wherein the first gate cut includes a same material as the gate spacer; and wherein a first width of the first gate cut is smaller than a second width of the gate spacer.

Abstract: A semiconductor device is provided.

Abstract: A semiconductor device includes a substrate, a first active pattern that includes a first side wall and a second side wall opposite to the first side wall in a second horizontal direction, a first insulating structure in a first trench extending in the first horizontal direction on the first side wall of the first active pattern, a second insulating structure in a second trench extending in the first horizontal direction on the second side of the first active pattern, and includes a first insulating layer on side walls and a bottom surface of the second trench, and a second insulating layer in the second trench on the first insulating layer, a gate-cut extending in the first horizontal direction on the first insulating structure, and a gate electrode extending in the second horizontal direction on the first active pattern.

Abstract: A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.

Abstract: A display device includes a first substrate defining a top surface thereof, a bottom surface thereof facing the top surface, and side surfaces thereof connecting the top and bottom surfaces to each other. The side surfaces included: a first side surface defined by: a first patterned surface including a first pattern of which a length thereof extends in a diagonal direction in a plan view of the first patterned surface, and a second patterned surface which extends obliquely from an upper end of the first patterned surface, the second patterned surface including a second pattern of which a length thereof extends in a perpendicular direction from the upper end of the first patterned surface in a plan view of the second patterned surface.

Abstract: Disclosed herein is a gas turbine and a method of cooling the same. A cooling air supply passage of extracting air out of a compressor of the gas turbine and diverting the air to the outside is formed, and vanes and blades of a turbine are cooled by such cooling air supply passage that does not pass through a central shaft of the gas turbine. Consequently, the consumption of cooling air may be reduced while cooling efficiency is not affected, and the flow rate of cooling air may be more easily controlled.

Abstract: A semiconductor device includes a substrate having an active pattern extending in a first direction, a first gate structure and a second gate structure extending in a second direction, intersecting the first direction, to traverse the active pattern, the first gate structure and the second gate structure isolated from each other while facing each other in the second direction, a gate isolation pattern disposed between the first gate structure and the second gate structure, the gate isolation pattern having a void, and a filling insulating portion positioned lower than upper surfaces of the first gate structure and the second gate structure within the gate isolation pattern, the filling insulating portion being connected to at least an upper end of the void.

Abstract: A display device includes a first substrate defining a top surface thereof, a bottom surface thereof facing the top surface, and side surfaces thereof connecting the top and bottom surfaces to each other. The side surfaces included: a first side surface defined by: a first patterned surface including a first pattern of which a length thereof extends in a diagonal direction in a plan view of the first patterned surface, and a second patterned surface which extends obliquely from an upper end of the first patterned surface, the second patterned surface including a second pattern of which a length thereof extends in a perpendicular direction from the upper end of the first patterned surface in a plan view of the second patterned surface.

Abstract: A semiconductor device includes a fin active region protruding from a substrate and extending in a first direction, a gate electrode covering an upper surface and sidewalls of the fin active region and extending in a second direction crossing the first direction, a gate spacer structure on opposite sidewalls of the gate electrode, an insulating capping layer on the gate electrode and extending in the second direction, an insulating liner on opposite sidewalls of the gate electrode and on an upper surface of the gate spacer structure, and a self-aligned contact at a side of the gate electrode. The insulating liner may have a second thickness greater than a first thickness of the gate spacer structure. A sidewall of the self-aligned contact may be in contact with the gate spacer structure and the insulating liner.

Abstract: A display device includes a first substrate defining a top surface thereof, a bottom surface thereof facing the top surface, and side surfaces thereof connecting the top and bottom surfaces to each other. The side surfaces included: a first side surface defined by: a first patterned surface including a first pattern of which a length thereof extends in a diagonal direction in a plan view of the first patterned surface, and a second patterned surface which extends obliquely from an upper end of the first patterned surface, the second patterned surface including a second pattern of which a length thereof extends in a perpendicular direction from the upper end of the first patterned surface in a plan view of the second patterned surface.

Abstract: A method of fabricating a semiconductor device is provided as follows. A strain relaxed buffer (SRB) layer is formed on a substrate. The SRB layer is formed of a first silicon germanium alloy (SiGe) layer which has a first atomic percent of germanium (Ge) atoms. A heterogeneous channel layer is formed on the SRB layer. The heterogeneous channel layer includes a silicon layer on a first region of the SRB layer and a second SiGe layer on a second region of the SRB layer. The second SiGe layer includes a second atomic percent of germanium greater than the first atomic percent of germanium atoms. The silicon layer is in contact with the second SiGe layer.

Abstract: A method of fabricating a semiconductor device is provided as follows. An epitaxial layer is formed on an active fin structure. Metal gate electrodes are formed on the active fin structure. Gate electrode caps are formed on upper surfaces of the metal gate electrodes. Metal gate spacers are formed on sidewalls of the metal gate electrodes. A source/drain electrode is formed on the epitaxial layer. An air spacer region is formed by removing the metal gate electrode caps and the metal gate spacers. An air spacer is formed within the air spacer region.

Abstract: A method of fabricating a semiconductor device is provided as follows. A channel layer is formed on a strain relaxed buffer (SRB) layer. A first etching process is performed on the channel layer and the SRB layer to form a plurality of trenches. The trenches penetrate through the channel layer and into the SRB layer to a first depth. First liners are formed on first sidewalls of the trenches having the first depth. The first liners cover the first sidewalls. A second etching process is performed on the SRB layer exposed through the trenches. The second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls.

Abstract: A display device includes a first substrate defining a top surface thereof, a bottom surface thereof facing the top surface, and side surfaces thereof connecting the top and bottom surfaces to each other. The side surfaces included: a first side surface defined by: a first patterned surface including a first pattern of which a length thereof extends in a diagonal direction in a plan view of the first patterned surface, and a second patterned surface which extends obliquely from an upper end of the first patterned surface, the second patterned surface including a second pattern of which a length thereof extends in a perpendicular direction from the upper end of the first patterned surface in a plan view of the second patterned surface.