Abstract: A circuit controls data input/output buffers, where an input buffer is disabled during a read mode for reducing power consumption. In a preferred embodiment, a data input buffer is enabled in response to a control signal to receive data from an input/output pad. A data output buffer provides data to the input/output pad in response to the control signal. A data input/output buffer control unit generates the control signal to disable the data input buffer and enable the data output buffer in read mode. Preferably, the circuit is readily applicable to a memory device, such as a Synchronous Dynamic Random Access Memory (SDRAM).

Abstract: A Column Address Strobe (CAS) latency control circuit for a SDRAM and a layout of the same allows an adequate CAS latency operation allowance at a high operation frequency. The SDRAM includes a plurality of banks each having ‘n’ main amplification units, ‘n’ bit data buses disposed between the plurality of banks each shared by respective main amplification units, ‘n’ CAS latency control circuits disposed concentrated central to the data buses one to one matched to the data buses, ‘n’ DQ blocks disposed connected to outputs of respective CAS latency control circuits in lengths different from one another, and a clock buffer for applying a clock signal to the CAS latency control circuits.

Abstract: A CAS latency control circuit for a SDRAM is provided for improving operation speeds of first and second CAS latencies. The circuit includes a controlling circuit unit for receiving a clock signal and providing first, second, third, and fourth control signals, a first latch for either passing or latching input data depending on the state of the first control signal, a second latch for either passing or latching the data from the first latching means depending on the state of the second control signal, a data pass selecting unit for forwarding either the data directly from the input or the data from the second latch depending on the state of the fourth control signal, and a third latch for either passing the data from the data pass selecting unit to the data output buffer or latching the data from the data pass selecting means depending on the state of the third control signal.