Patents by Inventor Dong-Kyum Kim
Dong-Kyum Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9905664Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.Type: GrantFiled: May 24, 2017Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Namkoong, Dong-Kyum Kim, Jung-Hwan Kim, Jung Geun Jee, Han-Vit Yang, Ji-Man Yoo
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Patent number: 9853044Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.Type: GrantFiled: January 14, 2016Date of Patent: December 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hoon Choi, Dong-Kyum Kim, Jin-Gyun Kim, Su-Jin Shin, Sang-Hoon Lee, Ki-Hyun Hwang
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Publication number: 20170278936Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.Type: ApplicationFiled: May 24, 2017Publication date: September 28, 2017Inventors: Hyun NAMKOONG, Dong-Kyum KIM, Jung-Hwan KIM, Jung Geun JEE, Han-Vit YANG, Ji-Man YOO
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Patent number: 9698231Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.Type: GrantFiled: February 3, 2016Date of Patent: July 4, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Namkoong, Dong-Kyum Kim, Jung-Hwan Kim, Jung Geun Jee, Han-Vit Yang, Ji-Man Yoo
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Patent number: 9613800Abstract: In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.Type: GrantFiled: February 18, 2015Date of Patent: April 4, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Yong Go, Jin-Gyun Kim, Dong-Kyum Kim, Jung-Ho Kim, Koong-Hyun Nam, Sung-Hae Lee, Eun-Young Lee, Jung-Geun Jee, Eun-Yeoung Choi, Ki-Hyun Hwang
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Patent number: 9536896Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.Type: GrantFiled: March 31, 2015Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoon Lee, Jin-Gyun Kim, Hyun Namkoong, Ki-Hyun Hwang, Hun-Hyeong Lim, Dong-Kyum Kim
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Publication number: 20160293618Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.Type: ApplicationFiled: February 3, 2016Publication date: October 6, 2016Inventors: Hyun NAMKOONG, Dong-Kyum KIM, Jung-Hwan KIM, Jung Geun JEE, Han-Vit YANG, Ji-Man YOO
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Patent number: 9368508Abstract: There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate.Type: GrantFiled: January 9, 2015Date of Patent: June 14, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Geun Jee, Dong Kyum Kim, Jin Gyun Kim, Ki Hyun Hwang
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Publication number: 20160133643Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.Type: ApplicationFiled: January 14, 2016Publication date: May 12, 2016Inventors: Ji-Hoon Choi, Dong-Kyum Kim, Jin-Gyun Kim, Su-Jin Shin, Sang-Hoon Lee, Ki-Hyun Hwang
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Publication number: 20160071877Abstract: A semiconductor device can include a single crystalline silicon substrate and a plurality of peripheral region circuits on the single crystalline silicon substrate. An insulating layer can be on the plurality of peripheral region circuits and a polycrystalline silicon substrate can be on the insulating layer, where the polycrystalline silicon substrate can include a first layer of the polycrystalline silicon substrate and an epi-second layer of the polycrystalline silicon substrate on the first layer. A plurality of memory cell circuits can be on the polycrystalline silicon substrate.Type: ApplicationFiled: September 4, 2015Publication date: March 10, 2016Inventors: DONG WOO KIM, DONG KYUM KIM, HUN HYEONG LIM, JUNG GEUN LEE
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Patent number: 9257573Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.Type: GrantFiled: July 24, 2013Date of Patent: February 9, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hoon Choi, Dong-Kyum Kim, Jin-Gyun Kim, Su-Jin Shin, Sang-Hoon Lee, Ki-Hyun Hwang
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Publication number: 20150372000Abstract: There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate.Type: ApplicationFiled: January 9, 2015Publication date: December 24, 2015Inventors: Jung Geun JEE, Dong Kyum KIM, Jin Gyun KIM, Ki Hyun HWANG
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Publication number: 20150235836Abstract: In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.Type: ApplicationFiled: February 18, 2015Publication date: August 20, 2015Inventors: Hyun-Yong GO, Jin-Gyun KIM, Dong-Kyum KIM, Jung-Ho KIM, Koong-Hyun NAM, Sung-Hae LEE, Eun-Young LEE, Jung-Geun JEE, Eun-Yeoung CHOI, Ki-Hyun HWANG
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Publication number: 20150206901Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Inventors: SANG-HOON LEE, JIN-GYUN KIM, KOONG-HYUN NAM, KI-HYUN HWANG, HUN-HYEONG LIM, DONG-KYUM KIM
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Patent number: 8994091Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.Type: GrantFiled: April 27, 2012Date of Patent: March 31, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Lee, Jin-Gyun Kim, Koong-Hyun Nam, Ki-Hyun Hwang, Hun-Hyeong Lim, Dong-Kyum Kim
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Publication number: 20140084357Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.Type: ApplicationFiled: July 24, 2013Publication date: March 27, 2014Inventors: Ji-Hoon Choi, Dong-Kyum Kim, Jin-Gyun Kim, Su-Jin Shin, Sang-Hoon Lee, Ki-Hyun Hwang
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Publication number: 20120280304Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.Type: ApplicationFiled: April 27, 2012Publication date: November 8, 2012Inventors: SANG-HOON LEE, JIN-GYUN KIM, KOONG-HYUN NAM, KI-HYUN HWANG, HUN-HYEONG LIM, DONG-KYUM KIM
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Publication number: 20120267702Abstract: A device includes a first GSL, a plurality of first word lines, a first SSL, a plurality of first insulation layer patterns, and a first channel. The first GSL, the first word lines, and the first SSL are spaced apart from each other on a substrate in a first direction perpendicular to a top surface of a substrate. The first insulation layer patterns are between the first GSL, the first word lines and the first SSL. The first channel on the top surface of the substrate extends in the first direction through the first GSL, the first word lines, the first SSL, and the first insulation layer patterns, and has a thickness thinner at a portion thereof adjacent to the first SSL than at portions thereof adjacent to the first insulation layer patterns.Type: ApplicationFiled: April 9, 2012Publication date: October 25, 2012Inventors: Jung-Geun JEE, Jin-Gyun Kim, Jun-Kyu Yang, Ji-Hoon Choi, Dong-Kyum Kim, Ki-Hyun Hwang