Patents by Inventor Dong Myoung Kim
Dong Myoung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145369Abstract: In one example, an electronic device comprises a substrate comprising a conductive structure and a dielectric structure, the dielectric structure comprising an upper dielectric layer, an electronic component over a top side of the substrate and coupled with the conductive structure, an encapsulant over the top side of the substrate and adjacent a lateral side of the electronic component, and a shield over the top side of the electronic component and contacting a lateral side of the encapsulant and a first lateral side of the substrate. The conductive structure comprises a first tab structure at the first lateral side of the substrate, and wherein the first tab structure contacts the shield and extends above the upper dielectric layer. Other examples and related methods are also disclosed herein.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Soo Hyun Kim, Won Myoung Ki, Dong Hoon Han, Tae Kyeong Hwang
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Publication number: 20240108536Abstract: A thermo-therapeutic apparatus and a method for controlling the same are provided.Type: ApplicationFiled: December 14, 2023Publication date: April 4, 2024Applicant: CERAGEM CO., LTDInventors: Dong Myoung LEE, Ki Sung KIM, Sang Cheol HAN, Jin Cheol PARK
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Patent number: 11948808Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.Type: GrantFiled: December 6, 2021Date of Patent: April 2, 2024Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Dong Jin Kim, Jin Han Kim, Won Chul Do, Jae Hun Bae, Won Myoung Ki, Dong Hoon Han, Do Hyung Kim, Ji Hun Lee, Jun Hwan Park, Seung Nam Son, Hyun Cho, Curtis Zwenger
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Patent number: 11728434Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.Type: GrantFiled: September 3, 2020Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Hoon Kim, Dong Myoung Kim, Dong Suk Shin, Seung Hun Lee, Cho Eun Lee, Hyun Jung Lee, Sung Uk Jang, Edward Nam Kyu Cho, Min-Hee Choi
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Publication number: 20220399330Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern.Type: ApplicationFiled: January 10, 2022Publication date: December 15, 2022Inventors: Kyung In Choi, Do Young Choi, Dong Myoung Kim, Jin Bum Kim, Hae Jun Yu
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Patent number: 11521678Abstract: The present invention relates to a synapse and synaptic array, and a computing system using the same. The synaptic device according to an exemplary embodiment of the present invention includes a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; and a plurality of two-terminal variable resistance memory devices in which a first electrode is electrically globally connected to a gate electrode of the transistor, wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes.Type: GrantFiled: August 18, 2021Date of Patent: December 6, 2022Assignee: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATIONInventors: Donguk Kim, Jun Tae Jang, Dae Hwan Kim, Dong Myoung Kim, Sung Jin Choi
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Publication number: 20220077314Abstract: Disclosed is a synaptic transistor, including a substrate, an expansion gate electrode disposed to extend in one direction on the substrate, a gate insulating layer including ions, covering the expansion gate electrode, and disposed on the substrate, a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode, source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer, and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.Type: ApplicationFiled: August 31, 2021Publication date: March 10, 2022Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATIONInventors: Dae Hwan KIM, Dong Yeon KANG, Jun Tae JANG, Shin Young PARK, Hyun Kyu LEE, Sung Jin CHOI, Dong Myoung KIM
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Publication number: 20220068379Abstract: The present invention relates to a synapse and synaptic array, and a computing system using the same. The synaptic device according to an exemplary embodiment of the present invention includes a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; and a plurality of two-terminal variable resistance memory devices in which a first electrode is electrically globally connected to a gate electrode of the transistor, wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes.Type: ApplicationFiled: August 18, 2021Publication date: March 3, 2022Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATIONInventors: Donguk KIM, Jun Tae JANG, Dae Hwan KIM, Dong Myoung KIM, Sung Jin CHOI
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Publication number: 20200403100Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Inventors: Seok Hoon KIM, Dong Myoung KIM, Dong Suk SHIN, Seung Hun LEE, Cho Eun LEE, Hyun Jung LEE, Sung Uk JANG, Edward Nam Kyu CHO, Min-Hee CHOI
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Patent number: 10784379Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.Type: GrantFiled: June 1, 2018Date of Patent: September 22, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Hoon Kim, Dong Myoung Kim, Dong Suk Shin, Seung Hun Lee, Cho Eun Lee, Hyun Jung Lee, Sung Uk Jang, Edward Nam Kyu Cho, Min-Hee Choi
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Patent number: 10672764Abstract: A semiconductor device includes a first region having a first active pattern with first protrusion portions and first recess portions, and a second region having a second active pattern with second protrusion portions and second recess portions. First gate patterns are on the first protrusion portions. Second gate patterns are on the second protrusion portions. A first source/drain region is on one of the first recess portion of the first active pattern between two of the first gate patterns. The first source/drain region has a first reinforcing epitaxial layer at an upper portion thereof. A second source/drain region is on one of the second recess portions of the second active pattern between two of the second gate patterns. The second source/drain region has a second reinforcing epitaxial layer having an epitaxial growth surface that is shaped differently than a first epitaxial growth surface of the first reinforcing epitaxial layer.Type: GrantFiled: October 30, 2018Date of Patent: June 2, 2020Assignee: Samsung Electroncis Co., Ltd.Inventors: Seok-hoon Kim, Dong-myoung Kim, Jin-bum Kim, Seung-hun Lee, Cho-eun Lee, Hyun-jung Lee, Sung-uk Jang, Edward Namkyu Cho, Min-hee Choi
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Publication number: 20190252376Abstract: A semiconductor device includes a first region having a first active pattern with first protrusion portions and first recess portions, and a second region having a second active pattern with second protrusion portions and second recess portions. First gate patterns are on the first protrusion portions. Second gate patterns are on the second protrusion portions. A first source/drain region is on one of the first recess portion of the first active pattern between two of the first gate patterns. The first source/drain region has a first reinforcing epitaxial layer at an upper portion thereof. A second source/drain region is on one of the second recess portions of the second active pattern between two of the second gate patterns. The second source/drain region has a second reinforcing epitaxial layer having an epitaxial growth surface that is shaped differently than a first epitaxial growth surface of the first reinforcing epitaxial layer.Type: ApplicationFiled: October 30, 2018Publication date: August 15, 2019Inventors: Seok-hoon Kim, Dong-myoung Kim, Jin-bum Kim, Seung-hun Lee, Cho-eun Lee, Hyun-jung Lee, Sung-uk Jang, Edward Namkyu Cho, Min-hee Choi
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Publication number: 20190067484Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.Type: ApplicationFiled: June 1, 2018Publication date: February 28, 2019Inventors: Seok Hoon KIM, Dong Myoung KIM, Dong Suk SHIN, Seung Hun LEE, Cho Eun LEE, Hyun Jung LEE, Sung Uk JANG, Edward Nam Kyu CHO, Min-Hee CHOI
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Patent number: 8989676Abstract: An apparatus and method perform Transmit Power Control and Dynamic Frequency Selection (TPC/DFS) during a movement of a Base Station (BS). A network environment around the mobile BS is modeled. Based on the modeling result, a TPC/DFS operation scheme that is most suitable to the mobile BS is selected.Type: GrantFiled: March 4, 2011Date of Patent: March 24, 2015Assignees: Samsung Electronics Co., Ltd., SNU R&DB FoundationInventors: Joseph Jeon, Sung-Hyun Choi, Kwang-Hun Han, Dong-Myoung Kim, Du-Ho Kang, Seung-Hyun Choi
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Patent number: 8761825Abstract: An apparatus and method for power control of a mobile BS of variable backbone capacity. The method includes determining a link state and capacity of a backbone of the BS, and determining a link state and service capacity between the BS and a mobile communication terminal. The method also includes, if the capacity of the backbone is less than the service capacity, setting the backbone capacity similar to the service capacity by lowering a transmit power of the BS by a predefined value.Type: GrantFiled: March 4, 2011Date of Patent: June 24, 2014Assignees: Samsung Electronics Co., Ltd., SNU R&DB FoundationInventors: Joseph Jeon, Sung-Hyun Choi, Kwang-Hun Han, Dong-Myoung Kim, Du-Ho Kang, Seung-Hyun Choi
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Publication number: 20110218013Abstract: An apparatus and method for power control of a mobile BS of variable backbone capacity. The method includes determining a link state and capacity of a backbone of the BS, and determining a link state and service capacity between the BS and a mobile communication terminal. The method also includes, if the capacity of the backbone is less than the service capacity, setting the backbone capacity similar to the service capacity by lowering a transmit power of the BS by a predefined value.Type: ApplicationFiled: March 4, 2011Publication date: September 8, 2011Applicants: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATIONInventors: Joseph Jeon, Sung-Hyun Choi, Kwang-Hun Han, Dong-Myoung Kim, Du-Ho Kang, Seung-Hyun Choi
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Publication number: 20110218005Abstract: An apparatus and method perform Transmit Power Control and Dynamic Frequency Selection (TPC/DFS) during a movement of a Base Station (BS). A network environment around the mobile BS is modeled. Based on the modeling result, a TPC/DFS operation scheme that is most suitable to the mobile BS is selected.Type: ApplicationFiled: March 4, 2011Publication date: September 8, 2011Applicants: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATIONInventors: Joseph Jeon, Sung-Hyun Choi, Kwang-Hun Han, Dong-Myoung Kim, Du-Ho Kang, Seung-Hyun Choi
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Patent number: 7166744Abstract: The present invention relates to a novel retinoid derivative compound represented by the formula I: wherein X, R1, R2 and R3 are as defined herein or pharmaceutically acceptalbe salts thereof. Also, the present invention relates to processes for producing the compound of the formula I and to an anti-cancer composition comprising the compound of the formula I. The compound of the formula I according to the present invention exerts high anti-cancer effects while not causing undesirable side effects.Type: GrantFiled: May 29, 2002Date of Patent: January 23, 2007Assignee: Chebigen Co., Ltd.Inventors: Hong-Sig Sin, Soo-Jong Um, Young-Soy Rho, Si-Ho Park, Youn-Ja Kwon, Myoung-Soon Park, Hye-Sook Han, So-Mi Kim, Dong-Myoung Kim, Deok-Kun Oh, Jong-Sup Park, Tae-Sung Bae
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Patent number: 6208860Abstract: An inter-cell hard hand-off timing determining method performs inter-cell hard hand-off by clearly determining a hand-off timing with a software method without assistance of hardware, thereby smoothly enabling traffic in a small base station that is installed in a shadow region or low traffic regions and reducing undesirable addition for hardware in increasing the small base station. The method is performed by the following steps of: identifying whether a mobile station has moved to a small base station; when it is determined that the mobile station has moved to the small base station, asking a selector and vocoder processing execution to report a power measurement report message having pilot signal strengths of an active set; reporting the PMRM to a call control execution; and when the mobile station is positioned at a boundary of a general base station, performing a inter-cell hard hand-off.Type: GrantFiled: December 17, 1998Date of Patent: March 27, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Yong Sin Kim, Dong Myoung Kim
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Patent number: 6154453Abstract: A method of selecting a vocoder in a CDMA mobile communication system, includes the steps of: indexing shelves, slots, and vocoders, before sequentially selecting a shelf and a slot according to the order of index, and, after detecting a frame offset of a present call, calculating a number of frame offsets identical with the frame offset of the present call contained in the selected slot; and comparing the number of the frame offsets, which are identical with the present call's frame offset and contained in the slot sequentially selected, with numbers of the identical frame offsets contained in other slots, and selecting a slot having the fewest frame offsets identical with the present call's frame offset.Type: GrantFiled: November 24, 1997Date of Patent: November 28, 2000Assignee: Hyundai Electronics Ind. Co., Ltd.Inventors: Jong-Woo Kim, Dong-Myoung Kim