Abstract: A motor drive system with a correction function of a temperature deviation of an IGBT module is provided. The system may include: a gate board configured to detect a plurality of sensing temperature information by sensing the IGBT module, acquire a difference value between maximum temperature information among the plurality of sensing temperature information and at least one sensing temperature information, and correct and output the at least one sensing temperature information by using the acquired difference value.

Abstract: A real time clock device for a vehicle may include: a register set provided with a first register, in which second time information is stored, and configured to store Real Time Clock (RTC) data including the time or date; and a data compensation circuit to block an input of a 1 second (1 s) tick to the first register and compensate for a delay time according to the block of the input of the 1 s tick to the first register by an RTC lock signal during a process of transmitting the RTC data to an external device or receiving setting data for the RTC data from the external device.

Abstract: A motor drive system with a correction function of a temperature deviation of an IGBT module is provided. The system may include: a gate board configured to detect a plurality of sensing temperature information by sensing the IGBT module, acquire a difference value between maximum temperature information among the plurality of sensing temperature information and at least one sensing temperature information, and correct and output the at least one sensing temperature information by using the acquired difference value.

Abstract: A multi-master system includes a first master, a second master, and an integrated control circuit controlled by each of the first and second masters. The integrated control circuit includes a first dedicated block configured to provide a first function to the first master, a second dedicated block configured to provide a second function to the second master, and a global using block configured to provide a common function to each of the first and second masters.

Abstract: Provided is an operating method of a monitoring device configured to monitor a microcontroller unit including a plurality of cores. The operating method includes: transmitting a question message to a first core among the plurality of cores; receiving an answer message from a second core among the plurality of cores; determining whether an operation of the microcontroller unit is abnormal, by using the answer message; receiving answer messages from cores, except for the second core, among the plurality of cores when the operation of the microcontroller unit is abnormal; and detecting an error of each of the plurality of cores by using the received answer messages.

Abstract: A real time clock device for a vehicle may include: a register set provided with a first register, in which second time information is stored, and configured to store Real Time Clock (RTC) data including the time or date; and a data compensation circuit to block an input of a 1 second (1 s) tick to the first register and compensate for a delay time according to the block of the input of the 1 s tick to the first register by an RTC lock signal during a process of transmitting the RTC data to an external device or receiving setting data for the RTC data from the external device.

Abstract: A multi-master system includes a first master, a second master, and an integrated control circuit controlled by each of the first and second masters. The integrated control circuit includes a first dedicated block configured to provide a first function to the first master, a second dedicated block configured to provide a second function to the second master, and a global using block configured to provide a common function to each of the first and second masters.

Abstract: Provided is an operating method of a monitoring device configured to monitor a microcontroller unit including a plurality of cores. The operating method includes: transmitting a question message to a first core among the plurality of cores; receiving an answer message from a second core among the plurality of cores; determining whether an operation of the microcontroller unit is abnormal, by using the answer message; receiving answer messages from cores, except for the second core, among the plurality of cores when the operation of the microcontroller unit is abnormal; and detecting an error of each of the plurality of cores by using the received answer messages.