Patents by Inventor Dong-Ren Peng

Dong-Ren Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948721
    Abstract: An apparatus includes a laminate, the laminate including a dielectric layer having a first surface and a second surface opposed to the first surface, and a conductive layer forming a circuit element overlying the first surface of the dielectric layer. The apparatus further includes a magnetic layer over the conductive layer. A first edge surface of the magnetic layer is coplanar with a first edge surface of the laminate, and a second edge surface of the magnetic layer is coplanar with a second edge surface of the laminate.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: April 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ying-Chuan Kao, Hung-Yu Chou, Dong-Ren Peng, Jun Jie Kuo, Kenji Otake, Chih-Chien Ho
  • Patent number: 11862538
    Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chung-Hao Lin, Hung-Yu Chou, Bo-Hsun Pan, Dong-Ren Peng, Pi-Chiang Huang, Yuh-Harng Chien
  • Publication number: 20230063262
    Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Chung-Hao LIN, Hung-Yu CHOU, Bo-Hsun PAN, Dong-Ren PENG, Pi-Chiang HUANG, Yuh-Harng CHIEN
  • Publication number: 20210375525
    Abstract: An apparatus includes a laminate, the laminate including a dielectric layer having a first surface and a second surface opposed to the first surface, and a conductive layer forming a circuit element overlying the first surface of the dielectric layer. The apparatus further includes a magnetic layer over the conductive layer. A first edge surface of the magnetic layer is coplanar with a first edge surface of the laminate, and a second edge surface of the magnetic layer is coplanar with a second edge surface of the laminate.
    Type: Application
    Filed: May 26, 2020
    Publication date: December 2, 2021
    Inventors: Ying-Chuan Kao, Hung-Yu Chou, Dong-Ren Peng, Jun Jie Kuo, Kenji Otake, Chih-Chien Ho