Abstract: A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values.

Abstract: A memory system includes a memory device comprising a plurality of memory blocks each memory block having N word line groups, N being a natural number equal to or more than 2; and a controller suitable for: selecting bad memory blocks among the memory blocks; arranging normal word line groups of the selected bad memory blocks into one or more memory-block-word-line groups each including non-conflicting N normal word line groups; and managing each of the memory-block-word-line groups as a reused memory block, the controller manages a reused block mapping table including a plurality of entries respectively corresponding to the memory-block-word-line groups, the reused block mapping table includes a plurality of logical addresses respectively corresponding to the entries, and each of the entries includes a plurality of physical address values respectively corresponding to the selected bad memory blocks having the normal word line groups included in the corresponding memory-block-word-line group.

Abstract: There are provided a controller coupled to a semiconductor memory device and an operating method thereof. A controller having improved operation speed includes a command generation unit for generating commands to be performed by a semiconductor memory device, a command queue for storing the commands and providing at least one command among the stored commands to the semiconductor memory device, and a command removal unit for, if the semiconductor memory device fails in the performance of the at least one command output from the main command queue, removing the at least one command and related commands of the at least one command from the command queue.

Abstract: A solenoid valve includes a valve that regulates the entrance and exit of oil, and a solenoid that operates the valve. The valve includes a hollow holder extending in one direction, ports including a supply port, a control port, and a discharge port, a passage that is formed in the holder and extends in the longitudinal direction of the holder, wherein a chamber connecting the supply port and the discharge port is formed in the middle of the passage, a spool movably installed in the passage, a channel that is formed in the spool and has one end connected to the control port and the other end connected to the chamber, a control land that divides the chamber into a supply chamber and a discharge chamber, and a spring that is installed between the holder and the spool to elastically support the spool.

Abstract: There are provided a controller of a semiconductor memory device, which stores data for debug processing, and an operating method of the controller. A controller for controlling a semiconductor memory device includes an event occurrence detection unit configured to detect whether an event occurs, an event information generation unit configured to generate event information in response to the detecting result from the event occurrence detection unit, and a command generation unit configured to generate a command for storing the event information in the semiconductor memory device.

Abstract: There are provided a controller coupled to a semiconductor memory device and an operating method thereof. A controller having improved operation speed includes a command generation unit for generating commands to be performed by a semiconductor memory device, a command queue for storing the commands and providing at least one command among the stored commands to the semiconductor memory device, and a command removal unit for, if the semiconductor memory device fails in the performance of the at least one command output from the main command queue, removing the at least one command and related commands of the at least one command from the command queue.

Abstract: A method of operating a controller includes, determining whether an address corresponding to a program operation indicates a lower page or an upper page; waiting for a first waiting time for the program operation to the lower page when the address indicates the lower page; waiting for a second waiting time for the program operation to the upper page when the address indicates the upper page, wherein the second waiting time is longer than the first waiting time; and performing a status read operation on the semiconductor memory device after one of the first waiting time or the second waiting time.

Abstract: A controller includes a command generation unit suitable for generating a first read command for at least one page selected from said plurality of pages, an error correction block suitable for performing a first error correction operation to one or more code words stored in said at least one selected page in response to the first read command, and a command mirroring unit suitable for generating a mirrored command by mirroring the first read command.

Abstract: It is an aspect of the present disclosure to provide a dish washing machine capable of actively responding to a problem when circulation of washing water is not smoothly performed by sequentially and selectively performing a bubble removal operation, a filter blockage removal operation, and a water supply operation, and a method of controlling the same.

Abstract: An operating method for controlling a semiconductor memory device according to an embodiment may include storing read commands in a command queue managed on first-in first-out basis; providing one of the read commands to the semiconductor memory device; determining whether the provided read command passes or fails based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting remaining read commands in the command queue when the provided read command passes.

Abstract: An operating method for controlling a semiconductor memory device according to an embodiment may include storing read commands in a command queue managed on first-in first-out basis; providing one of the read commands to the semiconductor memory device; determining whether the provided read command passes or fails based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting remaining read commands in the command queue when the provided read command passes.

Abstract: A memory system includes a semiconductor memory device including a plurality of ways suitable for storing normal data and reading stored data, and a system way suitable for storing system data, and a controller suitable for controlling the semiconductor memory device to perform overall operations of the plurality of ways and an update operation of the system data of the system way.

Abstract: A method of operating a controller includes, determining whether an address corresponding to a program operation indicates a lower page or an upper page; waiting for a first waiting time for the program operation to the lower page when the address indicates the lower page; waiting for a second waiting time for the program operation to the upper page when the address indicates the upper page, wherein the second waiting time is longer than the first waiting time; and performing a status read operation on the semiconductor memory device after one of the first waiting time or the second waiting time.

Abstract: An oil pump control valve assembly includes a control valve for controlling a flow of a fluid, and a solenoid for operating the control valve. The control valve includes a tube-like holder having a hollow internal space, configured to include an inflow port formed at one end thereof, a tube-like first valve sheet formed in the middle of the holder, a ball valve mounted in the first valve sheet, a second valve sheet coupled to a second end of the first valve sheet, and a load mounted in the second valve sheet, one end thereof being extended through the second valve sheet to come into contact with the ball valve, wherein, when the solenoid is operated, the ball valve is moved to open the inflow port.

Abstract: A liquid crystal display device includes first and second substrates spaced apart from and facing each other, gate and data lines on an inner surface of the first substrate and crossing each other to define a pixel region, a thin film transistor adjacent to the crossing of the gate and data lines, a pixel electrode in the pixel region and including a plurality of slits, an island pattern over the gate line, a black matrix on an inner surface of the second substrate, the black matrix corresponding to the gate line, a color filter layer on the black matrix, a common electrode on the color filter layer, a plurality of ribs on the common electrode corresponding to the pixel electrode; and a spacer on the common electrode corresponding to the black matrix.

Abstract: A vehicle lamp device is provided and includes a housing having an accommodating portion with an open side and a connector pin disposed in the accommodating portion. A light source unit is disposed in the accommodating portion and includes one or more light sources configured to irradiate light toward the open side of the accommodating portion. Additionally, a lens is coupled to the open side of the accommodating portion and is configured to transmit light irradiated from the light sources. The connector pin is integrally formed with the housing by insert injection, and the light source unit includes a printed circuit board (PCB) having an aperture through which an end of the connector pin passes and the light sources which are installed on the PCB and irradiate light.

Abstract: A liquid crystal display device includes first and second substrates spaced apart from and facing each other, gate and data lines on an inner surface of the first substrate and crossing each other to define a pixel region, a thin film transistor adjacent to the crossing of the gate and data lines, a pixel electrode in the pixel region and including a plurality of slits, an island pattern over the gate line, a black matrix on an inner surface of the second substrate, the black matrix corresponding to the gate line, a color filter layer on the black matrix, a common electrode on the color filter layer, a plurality of ribs on the common electrode corresponding to the pixel electrode; and a spacer on the common electrode corresponding to the black matrix.

Abstract: A solenoid valve includes a valve configured to control a flow of a fluid; and a solenoid configured to operate the valve. The valve includes: a holder having a double tube structure including an inner tube formed with a supply passage and an outer tube, a control passage being formed between the inner tube and the outer tube; a first connection port formed at a first end of the inner tube to connect the supply passage and the control passage; a ball installed within the supply passage to open and close the first connection port; a core coupled to a first end of the outer tube; a second connection port formed in the core and connected to the control passage; and a load installed to extend through the second connection port and moved by the solenoid.

Abstract: A liquid crystal display device includes first and second substrates spaced apart from and facing each other, gate and data lines on an inner surface of the first substrate and crossing each other to define a pixel region, a thin film transistor adjacent to the crossing of the gate and data lines, a pixel electrode in the pixel region and including a plurality of slits, an island pattern over the gate line, a black matrix on an inner surface of the second substrate, the black matrix corresponding to the gate line, a color filter layer on the black matrix, a common electrode on the color filter layer, a plurality of ribs on the common electrode corresponding to the pixel electrode; and a spacer on the common electrode corresponding to the black matrix.

Abstract: The present invention relates to an oil control valve for a variable valve lift system that obtains in a stable manner a constant hydraulic pressure in the hydraulic line connecting the oil control valve and the vale lift control actuator, and thereby reliably controls valve lift according to the number of revolutions and load of the engine.